@@ -16888,7 +16888,7 @@ rs6000_emit_vector_cond_expr (rtx dest,
op_false = tmp;
}
- cond2 = gen_rtx_fmt_ee (NE, cc_mode, mask, const0_rtx);
+ cond2 = gen_rtx_fmt_ee (NE, cc_mode, mask, CONST0_RTX (dest_mode));
emit_insn (gen_rtx_SET (VOIDmode,
dest,
gen_rtx_IF_THEN_ELSE (dest_mode,
@@ -465,21 +465,21 @@ (define_expand "vector_select_<mode>"
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
(if_then_else:VEC_L
(ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
- (const_int 0))
+ (match_dup 4))
(match_operand:VEC_L 2 "vlogical_operand" "")
(match_operand:VEC_L 1 "vlogical_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "")
+ "operands[4] = CONST0_RTX (<MODE>mode);")
(define_expand "vector_select_<mode>_uns"
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
(if_then_else:VEC_L
(ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
- (const_int 0))
+ (match_dup 4))
(match_operand:VEC_L 2 "vlogical_operand" "")
(match_operand:VEC_L 1 "vlogical_operand" "")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "")
+ "operands[4] = CONST0_RTX (<MODE>mode);")
;; Expansions that compare vectors producing a vector result and a predicate,
;; setting CR6 to indicate a combined status
@@ -487,7 +487,7 @@ (define_insn "*altivec_vsel<mode>"
[(set (match_operand:VM 0 "altivec_register_operand" "=v")
(if_then_else:VM
(ne:CC (match_operand:VM 1 "altivec_register_operand" "v")
- (const_int 0))
+ (match_operand:VM 4 "zero_constant" ""))
(match_operand:VM 2 "altivec_register_operand" "v")
(match_operand:VM 3 "altivec_register_operand" "v")))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
@@ -498,7 +498,7 @@ (define_insn "*altivec_vsel<mode>_uns"
[(set (match_operand:VM 0 "altivec_register_operand" "=v")
(if_then_else:VM
(ne:CCUNS (match_operand:VM 1 "altivec_register_operand" "v")
- (const_int 0))
+ (match_operand:VM 4 "zero_constant" ""))
(match_operand:VM 2 "altivec_register_operand" "v")
(match_operand:VM 3 "altivec_register_operand" "v")))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
@@ -674,7 +674,7 @@ (define_insn "*vsx_xxsel<mode>"
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
(if_then_else:VSX_L
(ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
- (const_int 0))
+ (match_operand:VSX_L 4 "zero_constant" ""))
(match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -685,7 +685,7 @@ (define_insn "*vsx_xxsel<mode>_uns"
[(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
(if_then_else:VSX_L
(ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
- (const_int 0))
+ (match_operand:VSX_L 4 "zero_constant" ""))
(match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
(match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -0,0 +1,24 @@
+/* PR target/49621 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -maltivec" } */
+
+#include <altivec.h>
+
+int
+foo (void)
+{
+ vector unsigned a, b, c;
+ unsigned k = 1;
+
+ a = (vector unsigned) { 0, 0, 0, 1 };
+ b = c = (vector unsigned) { 0, 0, 0, 0 };
+
+ a = vec_add (a, vec_splats (k));
+ b = vec_add (b, a);
+ c = vec_sel (c, a, b);
+
+ if (vec_any_eq (b, c))
+ return 1;
+
+ return 0;
+}