| Message ID | 20110601164906.2e4826c7@rex.config |
|---|---|
| State | New |
| Headers | show |
On Wed, 2011-06-01 at 16:49 +0100, Julian Brown wrote: > This patch tweaks the behaviour of arm_final_prescan_insn when tuning > for Cortex-A5 cores, since branches are cheaper than long sequences of > conditionalised instructions on those processors. As posted in the > previous patch, this provides a measurable increase in performance on a > popular embedded benchmark. > > (I didn't use the tuning infrastructure for this one, though it could > easily be changed to do so, now I come to think of it.) > > Testing is still in progress. OK to apply, pending success with that? > > Thanks, > > Julian > > ChangeLog > > gcc/ > * config/arm/arm.c (arm_tune_cortex_a5): New variable. > (arm_option_override): Use above. Set max_insns_skipped to 1 when > tuning for Cortex-A5. > * config/arm/arm.h (arm_tune_cortex_a5): Add declaration. I would much prefer that this was done through the tuning infrastructure. If one core likes it this way, there's a strong chance of another one coming along that has similar preferences. R.
commit 094f41f1d05322d24b76c7a680219a8549a9e717
Author: Julian Brown <julian@henry7.codesourcery.com>
Date: Fri May 27 11:26:57 2011 -0700
Tune max_insns_skipped for conditionalization for Cortex-A5.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index cd3f104..22b2a1d 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -763,6 +763,9 @@ int arm_tune_xscale = 0;
This typically means an ARM6 or ARM7 with MMU or MPU. */
int arm_tune_wbuf = 0;
+/* Nonzero if tuning for Cortex-A5. */
+int arm_tune_cortex_a5 = 0;
+
/* Nonzero if tuning for Cortex-A9. */
int arm_tune_cortex_a9 = 0;
@@ -1495,6 +1498,7 @@ arm_option_override (void)
arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
+ arm_tune_cortex_a5 = (arm_tune == cortexa5) != 0;
arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
/* If we are not using the default (ARM mode) section anchor offset
@@ -1737,6 +1741,11 @@ arm_option_override (void)
that is worth skipping is shorter. */
if (arm_tune_strongarm)
max_insns_skipped = 3;
+
+ /* Branches can be dual-issued on Cortex-A5, so conditional execution is
+ less appealing. */
+ if (arm_tune_cortex_a5)
+ max_insns_skipped = 1;
}
/* Hot/Cold partitioning is not currently supported, since we can't
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index ae6b39c..f4c34c1 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -418,6 +418,9 @@ extern int arm_tune_xscale;
/* Nonzero if tuning for stores via the write buffer. */
extern int arm_tune_wbuf;
+/* Nonzero if tuning for Cortex-A5. */
+extern int arm_tune_cortex_a5;
+
/* Nonzero if tuning for Cortex-A9. */
extern int arm_tune_cortex_a9;
This patch tweaks the behaviour of arm_final_prescan_insn when tuning for Cortex-A5 cores, since branches are cheaper than long sequences of conditionalised instructions on those processors. As posted in the previous patch, this provides a measurable increase in performance on a popular embedded benchmark. (I didn't use the tuning infrastructure for this one, though it could easily be changed to do so, now I come to think of it.) Testing is still in progress. OK to apply, pending success with that? Thanks, Julian ChangeLog gcc/ * config/arm/arm.c (arm_tune_cortex_a5): New variable. (arm_option_override): Use above. Set max_insns_skipped to 1 when tuning for Cortex-A5. * config/arm/arm.h (arm_tune_cortex_a5): Add declaration.