From patchwork Wed Jun 1 15:24:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julian Brown X-Patchwork-Id: 98210 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id C99F9B6F8C for ; Thu, 2 Jun 2011 01:24:46 +1000 (EST) Received: (qmail 13227 invoked by alias); 1 Jun 2011 15:24:45 -0000 Received: (qmail 13217 invoked by uid 22791); 1 Jun 2011 15:24:43 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 01 Jun 2011 15:24:28 +0000 Received: (qmail 20000 invoked from network); 1 Jun 2011 15:24:28 -0000 Received: from unknown (HELO rex.config) (julian@127.0.0.2) by mail.codesourcery.com with ESMTPA; 1 Jun 2011 15:24:28 -0000 Date: Wed, 1 Jun 2011 16:24:23 +0100 From: Julian Brown To: gcc-patches@gcc.gnu.org, paul@codesourcery.com, rearnsha@arm.com, Ramana Radhakrishnan Subject: [PATCH, ARM] Make branch cost a tunable parameter Message-ID: <20110601162423.22a33c6a@rex.config> Mime-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This patch allows the BRANCH_COST macro to be altered for a given target using the ARM backend's tuning infrastructure. It's not easy to reduce the cost to e.g. a single integer or a set of integers (cores may have different branch costing characteristics for ARM vs. Thumb-2 mode for instance, as in the existing BRANCH_COST definition), so I've used a function pointer in the tuning structure for maximum flexibility. This patch just uses the same hook for all existing cores (i.e. it should result in unchanged behaviour). Later patches can then override the default in specific cases. Testing is still in progress. OK to apply, pending success with that? Thanks, Julian ChangeLog gcc/ * config/arm/arm-protos.h (tune_params): Add branch_cost hook. * config/arm/arm.c (arm_default_branch_cost): New. (arm_slowmul_tune, arm_fastmul_tune, arm_xscale_tune, arm_9e_tune) (arm_v6t2_tune, arm_cortex_tune, arm_cortex_a9_tune) (arm_fa726_tune): Set branch_cost field using arm_default_branch_cost. * config/arm/arm.h (BRANCH_COST): Use branch_cost hook from current_tune structure. * dojump.c (tm_p.h): Include file. commit 31c8614cbe32a81960c9d8634f2c06534492b515 Author: Julian Brown Date: Fri May 27 10:39:01 2011 -0700 Make branch cost a tunable parameter. diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 8e0d54d..c104d74 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -225,6 +225,7 @@ struct tune_params int l1_cache_size; int l1_cache_line_size; bool prefer_constant_pool; + int (*branch_cost) (bool, bool); }; extern const struct tune_params *current_tune; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 8c8982d..c7eb5b0 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -255,6 +255,7 @@ static bool arm_builtin_support_vector_misalignment (enum machine_mode mode, static void arm_conditional_register_usage (void); static reg_class_t arm_preferred_rename_class (reg_class_t rclass); static unsigned int arm_autovectorize_vector_sizes (void); +static int arm_default_branch_cost (bool, bool); /* Table of machine attributes. */ @@ -856,7 +857,8 @@ const struct tune_params arm_slowmul_tune = NULL, 3, /* Constant limit. */ ARM_PREFETCH_NOT_BENEFICIAL, - true /* Prefer constant pool. */ + true, /* Prefer constant pool. */ + arm_default_branch_cost }; const struct tune_params arm_fastmul_tune = @@ -865,7 +867,8 @@ const struct tune_params arm_fastmul_tune = NULL, 1, /* Constant limit. */ ARM_PREFETCH_NOT_BENEFICIAL, - true /* Prefer constant pool. */ + true, /* Prefer constant pool. */ + arm_default_branch_cost }; const struct tune_params arm_xscale_tune = @@ -874,7 +877,8 @@ const struct tune_params arm_xscale_tune = xscale_sched_adjust_cost, 2, /* Constant limit. */ ARM_PREFETCH_NOT_BENEFICIAL, - true /* Prefer constant pool. */ + true, /* Prefer constant pool. */ + arm_default_branch_cost }; const struct tune_params arm_9e_tune = @@ -883,7 +887,8 @@ const struct tune_params arm_9e_tune = NULL, 1, /* Constant limit. */ ARM_PREFETCH_NOT_BENEFICIAL, - true /* Prefer constant pool. */ + true, /* Prefer constant pool. */ + arm_default_branch_cost }; const struct tune_params arm_v6t2_tune = @@ -892,7 +897,8 @@ const struct tune_params arm_v6t2_tune = NULL, 1, /* Constant limit. */ ARM_PREFETCH_NOT_BENEFICIAL, - false /* Prefer constant pool. */ + false, /* Prefer constant pool. */ + arm_default_branch_cost }; /* Generic Cortex tuning. Use more specific tunings if appropriate. */ @@ -902,7 +908,8 @@ const struct tune_params arm_cortex_tune = NULL, 1, /* Constant limit. */ ARM_PREFETCH_NOT_BENEFICIAL, - false /* Prefer constant pool. */ + false, /* Prefer constant pool. */ + arm_default_branch_cost }; const struct tune_params arm_cortex_a9_tune = @@ -911,7 +918,8 @@ const struct tune_params arm_cortex_a9_tune = cortex_a9_sched_adjust_cost, 1, /* Constant limit. */ ARM_PREFETCH_BENEFICIAL(4,32,32), - false /* Prefer constant pool. */ + false, /* Prefer constant pool. */ + arm_default_branch_cost }; const struct tune_params arm_fa726te_tune = @@ -920,7 +928,8 @@ const struct tune_params arm_fa726te_tune = fa726te_sched_adjust_cost, 1, /* Constant limit. */ ARM_PREFETCH_NOT_BENEFICIAL, - true /* Prefer constant pool. */ + true, /* Prefer constant pool. */ + arm_default_branch_cost }; @@ -8080,6 +8089,15 @@ arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) return cost; } +static int +arm_default_branch_cost (bool speed_p, bool predictable_p ATTRIBUTE_UNUSED) +{ + if (TARGET_32BIT) + return (TARGET_THUMB2 && !speed_p) ? 1 : 4; + else + return (optimize > 0) ? 2 : 0; +} + static int fp_consts_inited = 0; /* Only zero is valid for VFP. Other values are also valid for FPA. */ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 62a814b..ae6b39c 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1947,8 +1947,8 @@ typedef struct /* Try to generate sequences that don't involve branches, we can then use conditional instructions */ #define BRANCH_COST(speed_p, predictable_p) \ - (TARGET_32BIT ? (TARGET_THUMB2 && !speed_p ? 1 : 4) \ - : (optimize > 0 ? 2 : 0)) + (current_tune->branch_cost (speed_p, predictable_p)) + /* Position Independent Code. */ /* We decide which register to use based on the compilation options and diff --git a/gcc/dojump.c b/gcc/dojump.c index 6437a1f..7606c15 100644 --- a/gcc/dojump.c +++ b/gcc/dojump.c @@ -36,6 +36,7 @@ along with GCC; see the file COPYING3. If not see #include "ggc.h" #include "basic-block.h" #include "output.h" +#include "tm_p.h" static bool prefer_and_bit_test (enum machine_mode, int); static void do_jump_by_parts_greater (tree, tree, int, rtx, rtx, int);