From patchwork Fri May 27 13:35:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 97681 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 61D0DB6F92 for ; Fri, 27 May 2011 23:35:54 +1000 (EST) Received: (qmail 15813 invoked by alias); 27 May 2011 13:35:52 -0000 Received: (qmail 15527 invoked by uid 22791); 27 May 2011 13:35:50 -0000 X-SWARE-Spam-Status: No, hits=-3.7 required=5.0 tests=AWL, BAYES_20, NO_DNS_FOR_FROM, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mga01.intel.com (HELO mga01.intel.com) (192.55.52.88) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 27 May 2011 13:35:32 +0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 27 May 2011 06:35:32 -0700 X-ExtLoop1: 1 Received: from gnu-6.sc.intel.com ([10.3.194.135]) by fmsmga002.fm.intel.com with ESMTP; 27 May 2011 06:35:32 -0700 Received: by gnu-6.sc.intel.com (Postfix, from userid 500) id 13B66180D86; Fri, 27 May 2011 06:35:32 -0700 (PDT) Date: Fri, 27 May 2011 06:35:32 -0700 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Subject: PATCH: PR rtl-optimization/49114: Reload failed to handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const_int))) Message-ID: <20110527133531.GA8659@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, When reload gets: (insn 588 587 589 28 (set (mem:DF (zero_extend:DI (plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) (const_int 8 [0x8]))) [4 MEM[base: b_96(D), index: D.15020_278, step: 8, offset: 0B]+0 S8 A64]) (reg:DF 340 [ D.14980 ])) spooles.c:291 106 {*movdf_internal_rex64} (expr_list:REG_DEAD (reg:DF 340 [ D.14980 ]) (nil))) it generates: Reloads for insn # 588 Reload 0: reload_in (DI) = (reg/v/f:DI 182 [ b ]) GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0) reload_in_reg: (reg/v/f:DI 182 [ b ]) reload_reg_rtx: (reg:DI 1 dx) Reload 1: reload_in (DI) = (zero_extend:DI (plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) (const_int 8 [0x8]))) GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0) reload_in_reg: (zero_extend:DI (plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) (const_int 8 [0x8]))) reload_reg_rtx: (reg:DI 1 dx) Reload 2: reload_out (DF) = (mem:DF (zero_extend:DI (plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) (const_int 8 [0x8]))) [4 MEM[base: b_96(D), index: D.15020_278, step: 8, offset: 0B]+0 S8 A64]) NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional reload_out_reg: (mem:DF (zero_extend:DI (plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) (const_int 8 [0x8]))) [4 MEM[base: b_96(D), index: D.15020_278, step: 8, offset: 0B]+0 S8 A64]) leads to (insn 1017 587 1020 34 (set (reg:DI 1 dx) (mem/c:DI (plus:DI (reg/f:DI 7 sp) (const_int 112 [0x70])) [5 %sfp+-208 S8 A64])) spooles.c:291 62 {*movdi_internal_rex64} (nil)) (insn 1020 1017 1022 34 (set (reg:SI 1 dx) (const_int 8 [0x8])) spooles.c:291 64 {*movsi_internal} (nil)) (insn 1022 1020 1023 34 (set (reg:SI 1 dx) (reg:SI 1 dx)) spooles.c:291 64 {*movsi_internal} (nil)) (insn 1023 1022 1024 34 (set (reg:SI 1 dx) (plus:SI (reg:SI 1 dx) (const_int 8 [0x8]))) spooles.c:291 248 {*lea_1_x32} (expr_list:REG_EQUIV (plus:SI (subreg:SI (reg:DI 1 dx) 0) (const_int 8 [0x8])) (nil))) (insn 1024 1023 588 34 (set (reg:DI 1 dx) (zero_extend:DI (reg:SI 1 dx))) spooles.c:291 112 {*zero_extendsidi2_rex64} (expr_list:REG_EQUIV (zero_extend:DI (plus:SI (subreg:SI (reg:DI 1 dx) 0) (const_int 8 [0x8]))) (nil))) (insn 588 1024 589 34 (set (mem:DF (reg:DI 1 dx) [4 MEM[base: b_96(D), index: D.15020_278, step: 8, offset: 0B]+0 S8 A64]) (reg:DF 0 ax [orig:340 D.14980 ] [340])) spooles.c:291 106 {*movdf_internal_rex64} (nil)) gen_load has if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG || (REG_P (op1) For (plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) (const_int 8 [0x8])) it swaps SUBREG and CONST_INT. It leads to wrong code. This patch checks if OP0 is SUBREG before swapping. OK for trunk? Thanks. H.J. ---- commit 1dfd59e2fbbea198d7f3e977b559b4f307b2a659 Author: H.J. Lu Date: Tue May 24 17:42:53 2011 -0700 Properly handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const_int))) diff --git a/gcc/ChangeLog.x32 b/gcc/ChangeLog.x32 index bf844ea..3a5b9e7 100644 --- a/gcc/ChangeLog.x32 +++ b/gcc/ChangeLog.x32 @@ -1,3 +1,9 @@ +2011-05-24 H.J. Lu + + PR rtl-optimization/49114 + * reload1.c (gen_reload): Properly handle + (set reg:X (plus:X (subreg:X (reg:Y) 0) (const_int))) + 2011-05-21 H.J. Lu PR rtl-optimization/49088 diff --git a/gcc/reload1.c b/gcc/reload1.c index 4a697c2..d618a29 100644 --- a/gcc/reload1.c +++ b/gcc/reload1.c @@ -8528,7 +8528,9 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type) code = optab_handler (add_optab, GET_MODE (out)); - if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG + if ((GET_CODE (op0) != SUBREG + && (CONSTANT_P (op1) || MEM_P (op1))) + || GET_CODE (op1) == SUBREG || (REG_P (op1) && REGNO (op1) >= FIRST_PSEUDO_REGISTER) || (code != CODE_FOR_nothing