From patchwork Thu Apr 28 22:42:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 93344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 154FA1007D7 for ; Fri, 29 Apr 2011 08:42:39 +1000 (EST) Received: (qmail 28456 invoked by alias); 28 Apr 2011 22:42:38 -0000 Received: (qmail 28438 invoked by uid 22791); 28 Apr 2011 22:42:35 -0000 X-SWARE-Spam-Status: No, hits=-1.3 required=5.0 tests=AWL, BAYES_00, NO_DNS_FOR_FROM, TW_FN, TW_VM, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from e6.ny.us.ibm.com (HELO e6.ny.us.ibm.com) (32.97.182.146) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 28 Apr 2011 22:42:18 +0000 Received: from d01relay03.pok.ibm.com (d01relay03.pok.ibm.com [9.56.227.235]) by e6.ny.us.ibm.com (8.14.4/8.13.1) with ESMTP id p3SMI3Po020981 for ; Thu, 28 Apr 2011 18:18:03 -0400 Received: from d01av01.pok.ibm.com (d01av01.pok.ibm.com [9.56.224.215]) by d01relay03.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p3SMgGIq070716 for ; Thu, 28 Apr 2011 18:42:16 -0400 Received: from d01av01.pok.ibm.com (loopback [127.0.0.1]) by d01av01.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p3SMgGwp023524 for ; Thu, 28 Apr 2011 18:42:16 -0400 Received: from hungry-tiger.westford.ibm.com (dyn9033037078.westford.ibm.com [9.33.37.78]) by d01av01.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id p3SMgGf8023517; Thu, 28 Apr 2011 18:42:16 -0400 Received: by hungry-tiger.westford.ibm.com (Postfix, from userid 500) id 554D1F7E6F; Thu, 28 Apr 2011 18:42:15 -0400 (EDT) Date: Thu, 28 Apr 2011 18:42:15 -0400 From: Michael Meissner To: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com Subject: [PATCH, committed, 4.6] Backport some recent powerpc patches from trunk to GCC 4.6 Message-ID: <20110428224214.GA21679@hungry-tiger.westford.ibm.com> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org I just backported the following patches from the trunk to the GCC 4.6 branch and committed them after doing a bootstrap and make check with no regressions. [gcc] 2011-04-28 Michael Meissner Backport from mainline 2011-04-01 Andrew Pinski Michael Meissner PR target/48262 * config/rs6000/vector.md (movmisalign): Allow for memory operands, as per the specifications. * config/rs6000/altivec.md (vec_extract_evenv4si): Correct modes. (vec_extract_evenv4sf): Ditto. (vec_extract_evenv8hi): Ditto. (vec_extract_evenv16qi): Ditto. (vec_extract_oddv4si): Ditto. [libcpp] 2011-04-28 Michael Meissner Backport from mainline 2011-03-18 Michael Meissner PR preprocessor/48192 * directives.c (do_ifdef): Do not consider conditional macros as being defined. (do_ifndef): Ditto. * expr.c (parse_defined): Ditto. [gcc/testsuite] 2011-04-28 Michael Meissner Backport from mainline 2011-03-22 Michael Meissner * gcc.dg/torture/vector-1.c: On powerpc add -fabi=altivec to avoid failure on 32-bit systems. * gcc.dg/torture/vector-2.c: Ditto. Backport from mainline 2011-03-21 Michael Meissner * gcc.dg/torture/va-arg-25.c: Add -mabi=altivec -maltivec for powerpc. PR target/48226 * gcc.target/powerpc/pr48226.c: New file. Index: gcc/testsuite/gcc.dg/torture/va-arg-25.c =================================================================== --- gcc/testsuite/gcc.dg/torture/va-arg-25.c (revision 173136) +++ gcc/testsuite/gcc.dg/torture/va-arg-25.c (working copy) @@ -3,6 +3,8 @@ /* { dg-do run } */ /* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */ /* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-options "-mabi=altivec -maltivec" { target { powerpc-*-* powerpc64-*-* } } } */ +/* { dg-require-effective-target vmx_hw { target { powerpc-*-* powerpc64--*-* } } } */ #include #include Index: gcc/testsuite/gcc.dg/torture/vector-1.c =================================================================== --- gcc/testsuite/gcc.dg/torture/vector-1.c (revision 173136) +++ gcc/testsuite/gcc.dg/torture/vector-1.c (working copy) @@ -3,6 +3,8 @@ /* { dg-do run } */ /* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */ /* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-options "-mabi=altivec" { target { powerpc-*-* powerpc64-*-* } } } */ +/* { dg-require-effective-target vmx_hw { target { powerpc-*-* powerpc64--*-* } } } */ #define vector __attribute__((vector_size(16) )) Index: gcc/testsuite/gcc.dg/torture/vector-2.c =================================================================== --- gcc/testsuite/gcc.dg/torture/vector-2.c (revision 173136) +++ gcc/testsuite/gcc.dg/torture/vector-2.c (working copy) @@ -3,6 +3,8 @@ /* { dg-do run } */ /* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */ /* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-options "-mabi=altivec" { target { powerpc-*-* powerpc64-*-* } } } */ +/* { dg-require-effective-target vmx_hw { target { powerpc-*-* powerpc64--*-* } } } */ #define vector __attribute__((vector_size(16) )) Index: gcc/config/rs6000/vector.md =================================================================== --- gcc/config/rs6000/vector.md (revision 173136) +++ gcc/config/rs6000/vector.md (working copy) @@ -872,8 +872,8 @@ (define_expand "vec_realign_load_" ;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned ;; since the load already handles it. (define_expand "movmisalign" - [(set (match_operand:VEC_N 0 "vfloat_operand" "") - (match_operand:VEC_N 1 "vfloat_operand" ""))] + [(set (match_operand:VEC_N 0 "nonimmediate_operand" "") + (match_operand:VEC_N 1 "any_operand" ""))] "VECTOR_MEM_VSX_P (mode) && TARGET_ALLOW_MOVMISALIGN" "") Index: gcc/config/rs6000/altivec.md =================================================================== --- gcc/config/rs6000/altivec.md (revision 173136) +++ gcc/config/rs6000/altivec.md (working copy) @@ -2430,7 +2430,7 @@ (define_insn "altivec_stvrxl" (define_expand "vec_extract_evenv4si" [(set (match_operand:V4SI 0 "register_operand" "") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "") (match_operand:V4SI 2 "register_operand" "")] UNSPEC_EXTEVEN_V4SI))] "TARGET_ALTIVEC" @@ -2463,7 +2463,7 @@ (define_expand "vec_extract_evenv4si" (define_expand "vec_extract_evenv4sf" [(set (match_operand:V4SF 0 "register_operand" "") - (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "") (match_operand:V4SF 2 "register_operand" "")] UNSPEC_EXTEVEN_V4SF))] "TARGET_ALTIVEC" @@ -2495,7 +2495,7 @@ (define_expand "vec_extract_evenv4sf" }") (define_expand "vec_extract_evenv8hi" - [(set (match_operand:V4SI 0 "register_operand" "") + [(set (match_operand:V8HI 0 "register_operand" "") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "") (match_operand:V8HI 2 "register_operand" "")] UNSPEC_EXTEVEN_V8HI))] @@ -2528,9 +2528,9 @@ (define_expand "vec_extract_evenv8hi" }") (define_expand "vec_extract_evenv16qi" - [(set (match_operand:V4SI 0 "register_operand" "") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "") - (match_operand:V16QI 2 "register_operand" "")] + [(set (match_operand:V16QI 0 "register_operand" "") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "") + (match_operand:V16QI 2 "register_operand" "")] UNSPEC_EXTEVEN_V16QI))] "TARGET_ALTIVEC" " @@ -2562,7 +2562,7 @@ (define_expand "vec_extract_evenv16qi" (define_expand "vec_extract_oddv4si" [(set (match_operand:V4SI 0 "register_operand" "") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "") (match_operand:V4SI 2 "register_operand" "")] UNSPEC_EXTODD_V4SI))] "TARGET_ALTIVEC" @@ -2595,7 +2595,7 @@ (define_expand "vec_extract_oddv4si" (define_expand "vec_extract_oddv4sf" [(set (match_operand:V4SF 0 "register_operand" "") - (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "") (match_operand:V4SF 2 "register_operand" "")] UNSPEC_EXTODD_V4SF))] "TARGET_ALTIVEC" Index: libcpp/directives.c =================================================================== --- libcpp/directives.c (revision 173136) +++ libcpp/directives.c (working copy) @@ -1819,7 +1819,12 @@ do_ifdef (cpp_reader *pfile) if (node) { - skip = node->type != NT_MACRO; + /* Do not treat conditional macros as being defined. This is due to + the powerpc and spu ports using conditional macros for 'vector', + 'bool', and 'pixel' to act as conditional keywords. This messes + up tests like #ifndef bool. */ + skip = (node->type != NT_MACRO + || ((node->flags & NODE_CONDITIONAL) != 0)); _cpp_mark_macro_used (node); if (!(node->flags & NODE_USED)) { @@ -1860,7 +1865,12 @@ do_ifndef (cpp_reader *pfile) if (node) { - skip = node->type == NT_MACRO; + /* Do not treat conditional macros as being defined. This is due to + the powerpc and spu ports using conditional macros for 'vector', + 'bool', and 'pixel' to act as conditional keywords. This messes + up tests like #ifndef bool. */ + skip = (node->type == NT_MACRO + && ((node->flags & NODE_CONDITIONAL) == 0)); _cpp_mark_macro_used (node); if (!(node->flags & NODE_USED)) { Index: libcpp/expr.c =================================================================== --- libcpp/expr.c (revision 173136) +++ libcpp/expr.c (working copy) @@ -720,10 +720,15 @@ parse_defined (cpp_reader *pfile) pfile->state.prevent_expansion--; + /* Do not treat conditional macros as being defined. This is due to the + powerpc and spu ports using conditional macros for 'vector', 'bool', and + 'pixel' to act as conditional keywords. This messes up tests like #ifndef + bool. */ result.unsignedp = false; result.high = 0; result.overflow = false; - result.low = node && node->type == NT_MACRO; + result.low = (node && node->type == NT_MACRO + && (node->flags & NODE_CONDITIONAL) == 0); return result; }