Index: gcc/testsuite/gcc.target/i386/pr48084-3.c
===================================================================
--- gcc/testsuite/gcc.target/i386/pr48084-3.c	(revision 0)
+++ gcc/testsuite/gcc.target/i386/pr48084-3.c	(revision 0)
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse3" } */
+
+void
+_mm_monitor (void const * __P, unsigned int __E, unsigned int __H)
+{
+   __builtin_ia32_monitor (__P, __E, __H);
+}
Index: gcc/testsuite/gcc.target/i386/pr48084-2.c
===================================================================
--- gcc/testsuite/gcc.target/i386/pr48084-2.c	(revision 0)
+++ gcc/testsuite/gcc.target/i386/pr48084-2.c	(revision 0)
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__));
+typedef char __v8qi __attribute__ ((__vector_size__ (8)));
+void
+_mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
+{
+    __builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P);
+}
Index: gcc/testsuite/gcc.target/i386/pr48084-4.c
===================================================================
--- gcc/testsuite/gcc.target/i386/pr48084-4.c	(revision 0)
+++ gcc/testsuite/gcc.target/i386/pr48084-4.c	(revision 0)
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -msse2" } */
+
+void
+_mm_clflush (void const *__A)
+{
+  __builtin_ia32_clflush (__A);
+}
Index: gcc/testsuite/gcc.target/i386/pr48084-1.c
===================================================================
--- gcc/testsuite/gcc.target/i386/pr48084-1.c	(revision 0)
+++ gcc/testsuite/gcc.target/i386/pr48084-1.c	(revision 0)
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__));
+typedef float __v2sf __attribute__ ((__vector_size__ (8)));
+typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef float __v4sf __attribute__ ((__vector_size__ (16)));
+void
+_mm_storeh_pi (__m64 *__P, __m128 __A)
+{
+  __builtin_ia32_storehps ((__v2sf *)__P, (__v4sf)__A);
+}
Index: gcc/testsuite/ChangeLog.x32
===================================================================
--- gcc/testsuite/ChangeLog.x32	(revision 170901)
+++ gcc/testsuite/ChangeLog.x32	(working copy)
@@ -1,5 +1,13 @@
 2011-03-11  H.J. Lu  <hongjiu.lu@intel.com>
 
+	PR target/48084
+	* gcc.target/i386/pr48084-1.c: New.
+	* gcc.target/i386/pr48084-2.c: Likewise.
+	* gcc.target/i386/pr48084-3.c: Likewise.
+	* gcc.target/i386/pr48084-4.c: Likewise.
+
+2011-03-11  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* gcc.target/i386/stackalign/return-3.c: Require ia32 instead
 	of ilp32.
 
Index: gcc/config/i386/i386.c
===================================================================
--- gcc/config/i386/i386.c	(revision 170899)
+++ gcc/config/i386/i386.c	(working copy)
@@ -27178,7 +27178,11 @@ ix86_expand_special_args_builtin (const 
       op = expand_normal (arg);
       gcc_assert (target == 0);
       if (memory)
-	target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
+	{
+	  if (GET_MODE (op) != Pmode)
+	    op = convert_to_mode (Pmode, op, 1);
+	  target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
+	}
       else
 	target = force_reg (tmode, op);
       arg_adjust = 1;
@@ -27449,6 +27453,8 @@ ix86_expand_builtin (tree exp, rtx targe
       mode1 = insn_data[icode].operand[1].mode;
       mode2 = insn_data[icode].operand[2].mode;
 
+      if (GET_MODE (op0) != Pmode)
+	op0 = convert_to_mode (Pmode, op0, 1);
       op0 = force_reg (Pmode, op0);
       op0 = gen_rtx_MEM (mode1, op0);
 
@@ -27481,7 +27487,11 @@ ix86_expand_builtin (tree exp, rtx targe
 	op0 = expand_normal (arg0);
 	icode = CODE_FOR_sse2_clflush;
 	if (!insn_data[icode].operand[0].predicate (op0, Pmode))
+	  {
+	    if (GET_MODE (op0) != Pmode)
+	      op0 = convert_to_mode (Pmode, op0, 1);
 	    op0 = copy_to_mode_reg (Pmode, op0);
+	  }
 
 	emit_insn (gen_sse2_clflush (op0));
 	return 0;
@@ -27494,7 +27504,11 @@ ix86_expand_builtin (tree exp, rtx targe
       op1 = expand_normal (arg1);
       op2 = expand_normal (arg2);
       if (!REG_P (op0))
-	op0 = copy_to_mode_reg (Pmode, op0);
+	{
+	  if (GET_MODE (op0) != Pmode)
+	    op0 = convert_to_mode (Pmode, op0, 1);
+	  op0 = copy_to_mode_reg (Pmode, op0);
+	}
       if (!REG_P (op1))
 	op1 = copy_to_mode_reg (SImode, op1);
       if (!REG_P (op2))
@@ -27574,7 +27588,11 @@ ix86_expand_builtin (tree exp, rtx targe
       op0 = expand_normal (arg0);
       icode = CODE_FOR_lwp_llwpcb;
       if (!insn_data[icode].operand[0].predicate (op0, Pmode))
-	op0 = copy_to_mode_reg (Pmode, op0);
+	{
+	  if (GET_MODE (op0) != Pmode)
+	    op0 = convert_to_mode (Pmode, op0, 1);
+	  op0 = copy_to_mode_reg (Pmode, op0);
+	}
       emit_insn (gen_lwp_llwpcb (op0));
       return 0;
 
Index: gcc/ChangeLog.x32
===================================================================
--- gcc/ChangeLog.x32	(revision 170900)
+++ gcc/ChangeLog.x32	(working copy)
@@ -1,5 +1,12 @@
 2011-03-11  H.J. Lu  <hongjiu.lu@intel.com>
 
+	PR target/48084
+	* config/i386/i386.c (ix86_expand_special_args_builtin): Convert
+	memory to Pmode if needed.
+	(ix86_expand_builtin): Likewise.
+
+2011-03-11  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* config/i386/i386.md (*movabs<mode>_1): Only allow for
 	TARGET_LP64.
 	(*movabs<mode>_2): Likewise.
