From patchwork Sat Mar 12 15:42:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 86522 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id DA695B6EEE for ; Sun, 13 Mar 2011 02:42:49 +1100 (EST) Received: (qmail 4112 invoked by alias); 12 Mar 2011 15:42:47 -0000 Received: (qmail 4103 invoked by uid 22791); 12 Mar 2011 15:42:46 -0000 X-SWARE-Spam-Status: No, hits=-1.4 required=5.0 tests=AWL, BAYES_00, NO_DNS_FOR_FROM, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 12 Mar 2011 15:42:41 +0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 12 Mar 2011 07:42:40 -0800 X-ExtLoop1: 1 Received: from gnu-4.sc.intel.com ([10.3.194.56]) by orsmga001.jf.intel.com with ESMTP; 12 Mar 2011 07:42:39 -0800 Received: by gnu-4.sc.intel.com (Postfix, from userid 500) id A4AC920372; Sat, 12 Mar 2011 07:42:39 -0800 (PST) Date: Sat, 12 Mar 2011 07:42:39 -0800 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Subject: [x32] PATCH: PR target/48084: [x32] internal compiler error: in copy_to_mode_reg, at explow.c:630 Message-ID: <20110312154239.GA31165@lucon.org> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, I checked in this patch tp convert memory to Pmode if needed. H.J. Index: gcc/testsuite/gcc.target/i386/pr48084-3.c =================================================================== --- gcc/testsuite/gcc.target/i386/pr48084-3.c (revision 0) +++ gcc/testsuite/gcc.target/i386/pr48084-3.c (revision 0) @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse3" } */ + +void +_mm_monitor (void const * __P, unsigned int __E, unsigned int __H) +{ + __builtin_ia32_monitor (__P, __E, __H); +} Index: gcc/testsuite/gcc.target/i386/pr48084-2.c =================================================================== --- gcc/testsuite/gcc.target/i386/pr48084-2.c (revision 0) +++ gcc/testsuite/gcc.target/i386/pr48084-2.c (revision 0) @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__)); +typedef char __v8qi __attribute__ ((__vector_size__ (8))); +void +_mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P) +{ + __builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P); +} Index: gcc/testsuite/gcc.target/i386/pr48084-4.c =================================================================== --- gcc/testsuite/gcc.target/i386/pr48084-4.c (revision 0) +++ gcc/testsuite/gcc.target/i386/pr48084-4.c (revision 0) @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -msse2" } */ + +void +_mm_clflush (void const *__A) +{ + __builtin_ia32_clflush (__A); +} Index: gcc/testsuite/gcc.target/i386/pr48084-1.c =================================================================== --- gcc/testsuite/gcc.target/i386/pr48084-1.c (revision 0) +++ gcc/testsuite/gcc.target/i386/pr48084-1.c (revision 0) @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__)); +typedef float __v2sf __attribute__ ((__vector_size__ (8))); +typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef float __v4sf __attribute__ ((__vector_size__ (16))); +void +_mm_storeh_pi (__m64 *__P, __m128 __A) +{ + __builtin_ia32_storehps ((__v2sf *)__P, (__v4sf)__A); +} Index: gcc/testsuite/ChangeLog.x32 =================================================================== --- gcc/testsuite/ChangeLog.x32 (revision 170901) +++ gcc/testsuite/ChangeLog.x32 (working copy) @@ -1,5 +1,13 @@ 2011-03-11 H.J. Lu + PR target/48084 + * gcc.target/i386/pr48084-1.c: New. + * gcc.target/i386/pr48084-2.c: Likewise. + * gcc.target/i386/pr48084-3.c: Likewise. + * gcc.target/i386/pr48084-4.c: Likewise. + +2011-03-11 H.J. Lu + * gcc.target/i386/stackalign/return-3.c: Require ia32 instead of ilp32. Index: gcc/config/i386/i386.c =================================================================== --- gcc/config/i386/i386.c (revision 170899) +++ gcc/config/i386/i386.c (working copy) @@ -27178,7 +27178,11 @@ ix86_expand_special_args_builtin (const op = expand_normal (arg); gcc_assert (target == 0); if (memory) - target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op)); + { + if (GET_MODE (op) != Pmode) + op = convert_to_mode (Pmode, op, 1); + target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op)); + } else target = force_reg (tmode, op); arg_adjust = 1; @@ -27449,6 +27453,8 @@ ix86_expand_builtin (tree exp, rtx targe mode1 = insn_data[icode].operand[1].mode; mode2 = insn_data[icode].operand[2].mode; + if (GET_MODE (op0) != Pmode) + op0 = convert_to_mode (Pmode, op0, 1); op0 = force_reg (Pmode, op0); op0 = gen_rtx_MEM (mode1, op0); @@ -27481,7 +27487,11 @@ ix86_expand_builtin (tree exp, rtx targe op0 = expand_normal (arg0); icode = CODE_FOR_sse2_clflush; if (!insn_data[icode].operand[0].predicate (op0, Pmode)) + { + if (GET_MODE (op0) != Pmode) + op0 = convert_to_mode (Pmode, op0, 1); op0 = copy_to_mode_reg (Pmode, op0); + } emit_insn (gen_sse2_clflush (op0)); return 0; @@ -27494,7 +27504,11 @@ ix86_expand_builtin (tree exp, rtx targe op1 = expand_normal (arg1); op2 = expand_normal (arg2); if (!REG_P (op0)) - op0 = copy_to_mode_reg (Pmode, op0); + { + if (GET_MODE (op0) != Pmode) + op0 = convert_to_mode (Pmode, op0, 1); + op0 = copy_to_mode_reg (Pmode, op0); + } if (!REG_P (op1)) op1 = copy_to_mode_reg (SImode, op1); if (!REG_P (op2)) @@ -27574,7 +27588,11 @@ ix86_expand_builtin (tree exp, rtx targe op0 = expand_normal (arg0); icode = CODE_FOR_lwp_llwpcb; if (!insn_data[icode].operand[0].predicate (op0, Pmode)) - op0 = copy_to_mode_reg (Pmode, op0); + { + if (GET_MODE (op0) != Pmode) + op0 = convert_to_mode (Pmode, op0, 1); + op0 = copy_to_mode_reg (Pmode, op0); + } emit_insn (gen_lwp_llwpcb (op0)); return 0; Index: gcc/ChangeLog.x32 =================================================================== --- gcc/ChangeLog.x32 (revision 170900) +++ gcc/ChangeLog.x32 (working copy) @@ -1,5 +1,12 @@ 2011-03-11 H.J. Lu + PR target/48084 + * config/i386/i386.c (ix86_expand_special_args_builtin): Convert + memory to Pmode if needed. + (ix86_expand_builtin): Likewise. + +2011-03-11 H.J. Lu + * config/i386/i386.md (*movabs_1): Only allow for TARGET_LP64. (*movabs_2): Likewise.