From patchwork Wed Dec 22 15:11:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Weigand X-Patchwork-Id: 76418 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 92FC5B6EF2 for ; Thu, 23 Dec 2010 02:11:27 +1100 (EST) Received: (qmail 11534 invoked by alias); 22 Dec 2010 15:11:21 -0000 Received: (qmail 11522 invoked by uid 22791); 22 Dec 2010 15:11:20 -0000 X-SWARE-Spam-Status: No, hits=-1.3 required=5.0 tests=AWL, BAYES_00, MSGID_FROM_MTA_HEADER, SPF_SOFTFAIL, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mtagate1.uk.ibm.com (HELO mtagate1.uk.ibm.com) (194.196.100.161) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 22 Dec 2010 15:11:15 +0000 Received: from d06nrmr1307.portsmouth.uk.ibm.com (d06nrmr1307.portsmouth.uk.ibm.com [9.149.38.129]) by mtagate1.uk.ibm.com (8.13.1/8.13.1) with ESMTP id oBMFBDl9025158 for ; Wed, 22 Dec 2010 15:11:13 GMT Received: from d06av02.portsmouth.uk.ibm.com (d06av02.portsmouth.uk.ibm.com [9.149.37.228]) by d06nrmr1307.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id oBMFBEqH3666080 for ; Wed, 22 Dec 2010 15:11:14 GMT Received: from d06av02.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id oBMFBCpR015935 for ; Wed, 22 Dec 2010 08:11:12 -0700 Received: from tuxmaker.boeblingen.de.ibm.com (tuxmaker.boeblingen.de.ibm.com [9.152.85.9]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with SMTP id oBMFBBh9015886 for ; Wed, 22 Dec 2010 08:11:11 -0700 Message-Id: <201012221511.oBMFBBh9015886@d06av02.portsmouth.uk.ibm.com> Received: by tuxmaker.boeblingen.de.ibm.com (sSMTP sendmail emulation); Wed, 22 Dec 2010 16:11:11 +0100 Subject: [commit, spu] Fix (latent) ICE in spu_expand_mov To: gcc-patches@sourceware.org Date: Wed, 22 Dec 2010 16:11:11 +0100 (CET) From: "Ulrich Weigand" MIME-Version: 1.0 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello, in a compiler build with Tom de Vries' new sign/zero extension elimination pass added (http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01529.html), I'm seeing frequent internal compiler errors on the SPU. The reason is that this new pass frequently generates move instructions whose destination is a sub-word lowpart subreg. Now the problem on the SPU is some of those subregs are not directly valid (e.g. a SImode lowpart of a DImode value cannot be implemented by just reinterpreting register contents, but requires an actual shift due to the way values are laid out in the 16-bit SPU registers). The SPU move expander attempts to rewrite moves to eliminate such invalid subregs. However, it expects them to occur only on the *source* of a move, never the destination. Interestingly enough, this apparently never happens in a compiler without the extension elimination pass. On the other hand, such move instructions seem to be valid RTL as far as I can see from the docs, so the SPU back- end really ought to support them ... The following patch fixes this problem by having the move expander simply remove the subreg and perform the move in the inner mode. This fixes the ICEs with the extension elimination pass. Tested with no regressions on spu-elf. Committed to mainline. Bye, Ulrich ChangeLog: * config/spu/spu.md ("mov"): Use nonimmediate_operand predicate for destination operand. * config/spu/spu.c (spu_expand_mov): If move destination is an invalid subreg, perform move in the subreg's inner mode instead. diff -urp gcc/config/spu.orig/spu.c gcc/config/spu/spu.c --- gcc/config/spu.orig/spu.c 2010-12-10 16:51:16.000000000 +0100 +++ gcc/config/spu/spu.c 2010-12-21 16:49:02.000000000 +0100 @@ -4572,7 +4572,13 @@ int spu_expand_mov (rtx * ops, enum machine_mode mode) { if (GET_CODE (ops[0]) == SUBREG && !valid_subreg (ops[0])) - abort (); + { + /* Perform the move in the destination SUBREG's inner mode. */ + ops[0] = SUBREG_REG (ops[0]); + mode = GET_MODE (ops[0]); + ops[1] = gen_lowpart_common (mode, ops[1]); + gcc_assert (ops[1]); + } if (GET_CODE (ops[1]) == SUBREG && !valid_subreg (ops[1])) { diff -urp gcc/config/spu.orig/spu.md gcc/config/spu/spu.md --- gcc/config/spu.orig/spu.md 2010-12-10 16:51:16.000000000 +0100 +++ gcc/config/spu/spu.md 2010-12-21 16:57:27.000000000 +0100 @@ -269,8 +269,8 @@ ;; mov (define_expand "mov" - [(set (match_operand:ALL 0 "spu_nonimm_operand" "=r,r,r,m") - (match_operand:ALL 1 "general_operand" "r,i,m,r"))] + [(set (match_operand:ALL 0 "nonimmediate_operand" "") + (match_operand:ALL 1 "general_operand" ""))] "" { if (spu_expand_mov(operands, mode))