@@ -9714,7 +9714,7 @@ (define_insn "*ashlsi3_cmp_zext"
(define_insn "*ashl<mode>3_cconly"
[(set (reg FLAGS_REG)
(compare
- (ashift:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
+ (ashift:SWI (match_operand:SWI 1 "register_operand" "0")
(match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
(const_int 0)))
(clobber (match_scratch:SWI 0 "=<r>"))]
@@ -9723,8 +9723,7 @@ (define_insn "*ashl<mode>3_cconly"
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
|| TARGET_DOUBLE_WITH_ADD)))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)"
+ && ix86_match_ccmode (insn, CCGOCmode)"
{
switch (get_attr_type (insn))
{
@@ -10081,7 +10080,7 @@ (define_insn "*<shiftrt_insn><mode>3_cco
[(set (reg FLAGS_REG)
(compare
(any_shiftrt:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "0")
+ (match_operand:SWI 1 "register_operand" "0")
(match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
(const_int 0)))
(clobber (match_scratch:SWI 0 "=<r>"))]
@@ -10089,8 +10088,7 @@ (define_insn "*<shiftrt_insn><mode>3_cco
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& TARGET_SHIFT1))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ && ix86_match_ccmode (insn, CCGOCmode)"
{
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
@@ -0,0 +1,12 @@
+/* PR target/46088 */
+/* { dg-do compile } */
+/* { dg-options "-Os -fnon-call-exceptions -fpeel-loops" } */
+
+extern void bar (void);
+
+void
+foo (int i)
+{
+ if (i >> 3)
+ bar ();
+}