diff mbox

Don't set -mfprnd on power5

Message ID 20101103174620.GA16777@hungry-tiger.westford.ibm.com
State New
Headers show

Commit Message

Michael Meissner Nov. 3, 2010, 5:46 p.m. UTC 
Off the list, David asked me to check the floating point conversion patches for
various machines to make sure we weren't generating instructions that aren't
implemented for various -mcpu=<cpu> targets.

I discovered that -mcpu=power5 was generating the FRIZ instruciton (and other
rounding instrucitons) that were added in ISA 2.04 (power5+).  This wasn't in
the fp conversion patches I just submitted, but in patches we submitted
earlier.  This patch restricts the (double)(long long) optimization to use FRIZ
to machines with FPRND, and does not set the FPRND flag for -mcpu=power5.

I have bootstraped the compiler with these tests, and done unit tests on a
power5 machine to make sure the FRIZ instruction is not generated.  My unit
test of doing all possible conversions and rounds works fine on the power5
machine.

Is this patch ok to apply?  Note, the patch won't apply cleanly to the target
attributes patch, since the enum got moved to file scope in that patch.

2010-11-03  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
	turn on ISA 2.04 rounding instructions for power5.

	* config/rs6000/rs6000.md (friz): Friz is an ISA 2.04 instruciton,
	not ISA 2.02.
diff mbox

Patch

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 166212)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -2569,7 +2569,8 @@  rs6000_option_override_internal (const c
   /* Masks for instructions set at various powerpc ISAs.  */
   enum {
     ISA_2_1_MASKS = MASK_MFCRF,
-    ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB | MASK_FPRND),
+    ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB),
+    ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND),
 
     /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't
        add ALTIVEC, since in general it isn't a win on power6.  In ISA 2.04,
@@ -2738,7 +2739,9 @@  rs6000_option_override_internal (const c
     target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit);
   else if (TARGET_CMPB)
     target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit);
-  else if (TARGET_POPCNTB || TARGET_FPRND)
+  else if (TARGET_FPRND)
+    target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit);
+  else if (TARGET_POPCNTB)
     target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit);
   else if (TARGET_ALTIVEC)
     target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit);
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 166212)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -7142,7 +7142,7 @@  (define_insn "fctiwuz_<mode>"
 (define_insn "*friz"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
 	(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
-  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_POPCNTB
+  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
    && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
    && !flag_trapping_math && TARGET_FRIZ"
   "friz %0,%1"