From patchwork Sun Aug 22 02:37:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaz Kojima X-Patchwork-Id: 62358 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id AAA8DB70D3 for ; Sun, 22 Aug 2010 12:38:10 +1000 (EST) Received: (qmail 30946 invoked by alias); 22 Aug 2010 02:38:08 -0000 Received: (qmail 30936 invoked by uid 22791); 22 Aug 2010 02:38:07 -0000 X-SWARE-Spam-Status: No, hits=-2.1 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_PASS, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mo11.iij4u.or.jp (HELO mo.iij4u.or.jp) (210.138.174.79) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 22 Aug 2010 02:38:00 +0000 Received: by mo.iij4u.or.jp (mo11) id o7M2buiE021298; Sun, 22 Aug 2010 11:37:56 +0900 Received: from localhost (238.152.138.210.bn.2iij.net [210.138.152.238]) by mbox.iij4u.or.jp (mbox10) id o7M2btRK000366; Sun, 22 Aug 2010 11:37:56 +0900 Date: Sun, 22 Aug 2010 11:37:55 +0900 (JST) Message-Id: <20100822.113755.25336379.kkojima@rr.iij4u.or.jp> To: Naveen.S@kpitcummins.com Cc: gcc-patches@gcc.gnu.org, Prafulla.Thakare@kpitcummins.com Subject: Re: [PATCH SH2A]: Add movml instruction From: Kaz Kojima In-Reply-To: <20100820.223349.256206233.kkojima@rr.iij4u.or.jp> References: <20100814.164808.113199119.kkojima@rr.iij4u.or.jp> <371569CBCFB2E745B891DBB88B2DFDDD19E014480B@KCINPUNHJCMS01.kpit.com> <20100820.223349.256206233.kkojima@rr.iij4u.or.jp> Mime-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org > If so, it would be better to use normal rtls which describe > the semantic of those movml insns accurately, like as the peepholes > in your previous patch. Another minor problem is that your patch gives wrong dwarf2 information with -g. Even if it might not be a big problem for the interrupt handlers, the correct debug information is better. The attached patch will give correct dwarf2 codes with -g, though it isn't tested except for gcc.dg/attr-isr.c. Does it work for you? Regards, kaz --- * config/sh/sh.c (push_regs): Emit movml for interrupt handler when possible. (sh_expand_epilogue): Likewise. * config/sh/sh.md (movml_push_banked): New insn. (movml_pop_banked): Likewise. diff -up ORIG/trunk/gcc/config/sh/sh.c trunk/gcc/config/sh/sh.c --- ORIG/trunk/gcc/config/sh/sh.c 2010-07-17 10:31:31.000000000 +0900 +++ trunk/gcc/config/sh/sh.c 2010-08-22 10:58:56.000000000 +0900 @@ -6407,9 +6407,50 @@ push_regs (HARD_REG_SET *mask, int inter /* Push banked registers last to improve delay slot opportunities. */ if (interrupt_handler) - for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) - if (TEST_HARD_REG_BIT (*mask, i)) - push (i); + { + bool use_movml = false; + + if (TARGET_SH2A) + { + unsigned int count = 0; + + for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) + if (TEST_HARD_REG_BIT (*mask, i)) + count++; + else + break; + + /* Use movml when all banked registers are pushed. */ + if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1) + use_movml = true; + } + + if (use_movml) + { + rtx x, mem, reg, set; + rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM); + + /* We must avoid scheduling multiple store insn with another + insns. */ + emit_insn (gen_blockage ()); + x = gen_movml_push_banked (sp_reg); + x = frame_insn (x); + for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) + { + mem = gen_rtx_MEM (SImode, plus_constant (sp_reg, i * 4)); + reg = gen_rtx_REG (SImode, i); + add_reg_note (x, REG_CFA_OFFSET, gen_rtx_SET (SImode, mem, reg)); + } + + set = gen_rtx_SET (SImode, sp_reg, plus_constant (sp_reg, - 32)); + add_reg_note (x, REG_CFA_ADJUST_CFA, set); + emit_insn (gen_blockage ()); + } + else + for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) + if (TEST_HARD_REG_BIT (*mask, i)) + push (i); + } /* Don't push PR register for an ISR with RESBANK attribute assigned. */ if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ()) @@ -7347,9 +7388,37 @@ sh_expand_epilogue (bool sibcall_p) delay slot. RTE switches banks before the ds instruction. */ if (current_function_interrupt) { - for (i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--) - if (TEST_HARD_REG_BIT (live_regs_mask, i)) - pop (i); + bool use_movml = false; + + if (TARGET_SH2A) + { + unsigned int count = 0; + + for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++) + if (TEST_HARD_REG_BIT (live_regs_mask, i)) + count++; + else + break; + + /* Use movml when all banked register are poped. */ + if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1) + use_movml = true; + } + + if (use_movml) + { + rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM); + + /* We must avoid scheduling multiple load insn with another + insns. */ + emit_insn (gen_blockage ()); + emit_insn (gen_movml_pop_banked (sp_reg)); + emit_insn (gen_blockage ()); + } + else + for (i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--) + if (TEST_HARD_REG_BIT (live_regs_mask, i)) + pop (i); last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1; } diff -up ORIG/trunk/gcc/config/sh/sh.md trunk/gcc/config/sh/sh.md --- ORIG/trunk/gcc/config/sh/sh.md 2010-07-13 23:39:56.000000000 +0900 +++ trunk/gcc/config/sh/sh.md 2010-08-22 09:59:38.000000000 +0900 @@ -9216,6 +9216,39 @@ mov.l\\t1f,r0\\n\\ "" [(set_attr "length" "0")]) +;; Define movml instructions for SH2A target. Currently they are +;; used to push and pop all banked registers only. + +(define_insn "movml_push_banked" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus (match_dup 0) (const_int -32))) + (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG)) + (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG)) + (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG)) + (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG)) + (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG)) + (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG)) + (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG)) + (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))] + "TARGET_SH2A && REGNO (operands[0]) == 15" + "movml.l\tr7,@-r15" + [(set_attr "in_delay_slot" "no")]) + +(define_insn "movml_pop_banked" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus (match_dup 0) (const_int 32))) + (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32)))) + (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28)))) + (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24)))) + (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20)))) + (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16)))) + (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12)))) + (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8)))) + (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))] + "TARGET_SH2A && REGNO (operands[0]) == 15" + "movml.l\t@r15+,r7" + [(set_attr "in_delay_slot" "no")]) + ;; ------------------------------------------------------------------------ ;; Scc instructions ;; ------------------------------------------------------------------------