From patchwork Thu Jun 10 11:26:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julian Brown X-Patchwork-Id: 55203 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 89032B7D4A for ; Thu, 10 Jun 2010 21:27:11 +1000 (EST) Received: (qmail 17636 invoked by alias); 10 Jun 2010 11:27:09 -0000 Received: (qmail 17626 invoked by uid 22791); 10 Jun 2010 11:27:08 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 10 Jun 2010 11:26:59 +0000 Received: (qmail 672 invoked from network); 10 Jun 2010 11:26:57 -0000 Received: from unknown (HELO rex.config) (julian@127.0.0.2) by mail.codesourcery.com with ESMTPA; 10 Jun 2010 11:26:57 -0000 Date: Thu, 10 Jun 2010 12:26:52 +0100 From: Julian Brown To: Richard Earnshaw Cc: gcc-patches@gcc.gnu.org, paul@codesourcery.com Subject: Re: [PATCH, ARM] Tweak CLASS_LIKELY_SPILLED_P, MODE_BASE_REG_CLASS for Thumb-2 Message-ID: <20100610122652.4dee6376@rex.config> In-Reply-To: <1275986693.6195.0.camel@e102346-lin.cambridge.arm.com> References: <20100528122322.607c237a@rex.config> <20100528122648.7fb88458@rex.config> <1275051869.12222.19.camel@e102346-lin.cambridge.arm.com> <20100607195716.0cded789@rex.config> <1275986693.6195.0.camel@e102346-lin.cambridge.arm.com> Mime-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Tue, 08 Jun 2010 09:44:53 +0100 Richard Earnshaw wrote: > > On Mon, 2010-06-07 at 19:57 +0100, Julian Brown wrote: > > On Fri, 28 May 2010 14:04:29 +0100 > > Richard Earnshaw wrote: > > > > > > > > On Fri, 2010-05-28 at 12:26 +0100, Julian Brown wrote: > > > > /* The class value for index registers, and the one for base > > > > regs. */ > > > > @@ -1260,7 +1263,7 @@ enum reg_class > > > > when addressing quantities in QI or HI mode; if we don't > > > > know the mode, then we must be conservative. */ > > > > #define > > > > MODE_BASE_REG_CLASS(MODE) \ > > > > - (TARGET_32BIT ? > > > > CORE_REGS : \ > > > > + (TARGET_32BIT ? (TARGET_THUMB2 ? LO_REGS : > > > > CORE_REGS) : \ > > > > (((MODE) == SImode) ? BASE_REGS : LO_REGS)) > > > > > > > > > > Why not change the first test to TARGET_ARM? > > > > (I think you mean like the attached patch.) > > ENOPATCH D'oh, sorry. Here it is. Julian Index: gcc/regrename.c =================================================================== --- gcc/regrename.c (revision 159320) +++ gcc/regrename.c (working copy) @@ -26,7 +26,6 @@ #include "tm_p.h" #include "insn-config.h" #include "regs.h" -#include "addresses.h" #include "hard-reg-set.h" #include "basic-block.h" #include "reload.h" @@ -34,6 +33,7 @@ #include "function.h" #include "recog.h" #include "flags.h" +#include "addresses.h" #include "toplev.h" #include "obstack.h" #include "timevar.h" Index: gcc/recog.c =================================================================== --- gcc/recog.c (revision 159320) +++ gcc/recog.c (working copy) @@ -31,10 +31,10 @@ along with GCC; see the file COPYING3. #include "hard-reg-set.h" #include "recog.h" #include "regs.h" -#include "addresses.h" #include "expr.h" #include "function.h" #include "flags.h" +#include "addresses.h" #include "real.h" #include "toplev.h" #include "basic-block.h" Index: gcc/config/arm/arm.h =================================================================== --- gcc/config/arm/arm.h (revision 159320) +++ gcc/config/arm/arm.h (working copy) @@ -1245,11 +1245,14 @@ enum reg_class || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ : 0) -/* We need to define this for LO_REGS on thumb. Otherwise we can end up - using r0-r4 for function arguments, r7 for the stack frame and don't - have enough left over to do doubleword arithmetic. */ +/* We need to define this for LO_REGS on Thumb-1. Otherwise we can end up + using r0-r4 for function arguments, r7 for the stack frame and don't have + enough left over to do doubleword arithmetic. For Thumb-2 all the + potentially problematic instructions accept high registers so this is not + necessary. Care needs to be taken to avoid adding new Thumb-2 patterns + that require many low registers. */ #define CLASS_LIKELY_SPILLED_P(CLASS) \ - ((TARGET_THUMB && (CLASS) == LO_REGS) \ + ((TARGET_THUMB1 && (CLASS) == LO_REGS) \ || (CLASS) == CC_REG) /* The class value for index registers, and the one for base regs. */ @@ -1260,7 +1263,7 @@ enum reg_class when addressing quantities in QI or HI mode; if we don't know the mode, then we must be conservative. */ #define MODE_BASE_REG_CLASS(MODE) \ - (TARGET_32BIT ? CORE_REGS : \ + (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ (((MODE) == SImode) ? BASE_REGS : LO_REGS)) /* For Thumb we can not support SP+reg addressing, so we return LO_REGS Index: gcc/regcprop.c =================================================================== --- gcc/regcprop.c (revision 159320) +++ gcc/regcprop.c (working copy) @@ -26,7 +26,6 @@ #include "tm_p.h" #include "insn-config.h" #include "regs.h" -#include "addresses.h" #include "hard-reg-set.h" #include "basic-block.h" #include "reload.h" @@ -34,6 +33,7 @@ #include "function.h" #include "recog.h" #include "flags.h" +#include "addresses.h" #include "toplev.h" #include "obstack.h" #include "timevar.h"