From patchwork Fri Oct 14 13:51:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 682286 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3swTZf6Hrmz9t1P for ; Sat, 15 Oct 2016 00:53:14 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=lSPYKVgU; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=Zrt/1bXiVvheV+sOA iub6xGDwjwPZ2PpBi6zaZjED/n5B9vIQBFZcUsrDWKUWfulp6uR1oyaxMde3W1aN MqEVOuVu07ABq6Lv8pEPDaBDRVCIZZ12JpLgfDEXH12rwlnj+9bc+bxMpTvq7ECK k6xuZjHIwxyS3xdi3ClwEWML6M= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=fzpmK7dpcQo5bYaHbSDSTak f4Bo=; b=lSPYKVgUvcCnFDRJYoMLJEDLS+HINl7pmlBWVoP8LYwLtO9upqPJBdp jDnQuTQntjyLTX94Sw2Yyk98oK6cG9twDa+KI/AtO4R4ikVPiQRvWsiLuoxUwilc a8OEsmGx1DAeEnV/MHpGJvh5IXvXDLfgmSkDjx6coQeodcc2xKCQ= Received: (qmail 77245 invoked by alias); 14 Oct 2016 13:51:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 77084 invoked by uid 89); 14 Oct 2016 13:51:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.7 required=5.0 tests=BAYES_50, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=1, 11, sk:CXXFLAG, sk:cxxflag, ARMv8A X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 14 Oct 2016 13:51:40 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 20A7B16; Fri, 14 Oct 2016 06:51:38 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 605BB3F32C; Fri, 14 Oct 2016 06:51:37 -0700 (PDT) Subject: Re: [PATCH, ARM 7/7, ping2] Enable ARMv8-M atomic and synchronization support for ARMv8-M Baseline To: "gcc-patches@gcc.gnu.org" , Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw References: From: Thomas Preudhomme Message-ID: <1e17ffdb-4ecf-1b99-9ed1-2354f338df77@foss.arm.com> Date: Fri, 14 Oct 2016 14:51:36 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: X-IsSubscribed: yes Ping? Best regards, Thomas On 03/10/16 17:46, Thomas Preudhomme wrote: > Ping? > > Best regards, > > Thomas > > On 22/09/16 14:50, Thomas Preudhomme wrote: >> Hi, >> >> This patch is part of a patch series to add support for atomic operations on >> ARMv8-M Baseline targets in GCC. This specific patch enables atomic and >> synchronization support added in previous patches of the series and adds tests. >> Enabling is done at the end of the patch series to ensure that no ICE is seen >> when in the middle of the patch series (eg. while doing a bisect). Enabling is >> done by enabling the exclusive and atomic loads and stores needed to implement >> all synchronization and atomic operations. >> >> ChangeLog entries are as follow: >> >> *** gcc/ChangeLog *** >> >> 2016-07-05 Thomas Preud'homme >> >> * config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline. >> (TARGET_HAVE_LDREXBH): Likewise. >> (TARGET_HAVE_LDACQ): Likewise. >> >> >> *** gcc/testsuite/ChangeLog *** >> >> 2016-07-05 Thomas Preud'homme >> >> * gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test. >> * gcc.target/arm/atomic-op-acq_rel-3.c: Likewise. >> * gcc.target/arm/atomic-op-acquire-3.c: Likewise. >> * gcc.target/arm/atomic-op-char-3.c: Likewise. >> * gcc.target/arm/atomic-op-consume-3.c: Likewise. >> * gcc.target/arm/atomic-op-int-3.c: Likewise. >> * gcc.target/arm/atomic-op-relaxed-3.c: Likewise. >> * gcc.target/arm/atomic-op-release-3.c: Likewise. >> * gcc.target/arm/atomic-op-seq_cst-3.c: Likewise. >> * gcc.target/arm/atomic-op-short-3.c: Likewise. >> >> >> Testing: No code generation difference for ARMv7-A, ARMv7VE and ARMv8-A on all >> atomic and synchronization testcases in the testsuite [2]. Patchset was also >> bootstrapped with --enable-itm --enable-gomp on ARMv8-A in ARM and Thumb mode at >> optimization level -O1 and above [1] without any regression in the testsuite and >> no code generation difference in libitm and libgomp. >> >> Code generation for ARMv8-M Baseline has been manually examined and compared >> against ARMv8-A Thumb-2 for the following configuration without finding any >> issue: >> >> gcc.dg/atomic-op-2.c at -Os >> gcc.dg/atomic-compare-exchange-2.c at -Os >> gcc.dg/atomic-compare-exchange-3.c at -O3 >> >> >> Is this ok for trunk? >> >> Best regards, >> >> Thomas >> >> [1] CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET were set to "-O1 -g", "-O3 -g" and >> undefined ("-O2 -g") >> [2] The exact list is: >> >> gcc/testsuite/gcc.dg/atomic-compare-exchange-1.c >> gcc/testsuite/gcc.dg/atomic-compare-exchange-2.c >> gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c >> gcc/testsuite/gcc.dg/atomic-exchange-1.c >> gcc/testsuite/gcc.dg/atomic-exchange-2.c >> gcc/testsuite/gcc.dg/atomic-exchange-3.c >> gcc/testsuite/gcc.dg/atomic-fence.c >> gcc/testsuite/gcc.dg/atomic-flag.c >> gcc/testsuite/gcc.dg/atomic-generic.c >> gcc/testsuite/gcc.dg/atomic-generic-aux.c >> gcc/testsuite/gcc.dg/atomic-invalid-2.c >> gcc/testsuite/gcc.dg/atomic-load-1.c >> gcc/testsuite/gcc.dg/atomic-load-2.c >> gcc/testsuite/gcc.dg/atomic-load-3.c >> gcc/testsuite/gcc.dg/atomic-lockfree.c >> gcc/testsuite/gcc.dg/atomic-lockfree-aux.c >> gcc/testsuite/gcc.dg/atomic-noinline.c >> gcc/testsuite/gcc.dg/atomic-noinline-aux.c >> gcc/testsuite/gcc.dg/atomic-op-1.c >> gcc/testsuite/gcc.dg/atomic-op-2.c >> gcc/testsuite/gcc.dg/atomic-op-3.c >> gcc/testsuite/gcc.dg/atomic-op-6.c >> gcc/testsuite/gcc.dg/atomic-store-1.c >> gcc/testsuite/gcc.dg/atomic-store-2.c >> gcc/testsuite/gcc.dg/atomic-store-3.c >> gcc/testsuite/g++.dg/ext/atomic-1.C >> gcc/testsuite/g++.dg/ext/atomic-2.C >> gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c >> gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c >> gcc/testsuite/gcc.target/arm/atomic-op-acquire.c >> gcc/testsuite/gcc.target/arm/atomic-op-char.c >> gcc/testsuite/gcc.target/arm/atomic-op-consume.c >> gcc/testsuite/gcc.target/arm/atomic-op-int.c >> gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c >> gcc/testsuite/gcc.target/arm/atomic-op-release.c >> gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c >> gcc/testsuite/gcc.target/arm/atomic-op-short.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c >> gcc/testsuite/gcc.target/arm/atomic_loaddi_9.c >> gcc/testsuite/gcc.target/arm/sync-1.c >> gcc/testsuite/gcc.target/arm/synchronize.c >> gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c >> gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c >> gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c >> gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c >> libstdc++-v3/testsuite/29_atomics/atomic/60658.cc >> libstdc++-v3/testsuite/29_atomics/atomic/62259.cc >> libstdc++-v3/testsuite/29_atomics/atomic/64658.cc >> libstdc++-v3/testsuite/29_atomics/atomic/65147.cc >> libstdc++-v3/testsuite/29_atomics/atomic/65913.cc >> libstdc++-v3/testsuite/29_atomics/atomic/70766.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/constexpr.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/copy_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/default.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/direct_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/single_value.cc >> libstdc++-v3/testsuite/29_atomics/atomic/cons/user_pod.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/51811.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/56011.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_assignment.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_conversion.cc >> libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc >> libstdc++-v3/testsuite/29_atomics/atomic/requirements/base_classes.cc >> libstdc++-v3/testsuite/29_atomics/atomic/requirements/compare_exchange_lowering.cc >> >> libstdc++-v3/testsuite/29_atomics/atomic/requirements/explicit_instantiation/1.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/clear/1.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/1.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/56012.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/aggregate.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/default.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/standard_layout.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/trivial.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/explicit.cc >> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/implicit.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/60940.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/65147.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/constexpr.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/copy_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/default.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/direct_list.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/single_value.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/bitwise.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/decrement.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/increment.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_assignment.cc >> >> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_conversion.cc >> >> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/standard_layout.cc >> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/trivial.cc >> libstdc++-v3/testsuite/29_atomics/headers/atomic/functions_std_c++0x.cc >> libstdc++-v3/testsuite/29_atomics/headers/atomic/macros.cc >> libstdc++-v3/testsuite/29_atomics/headers/atomic/types_std_c++0x.cc diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index c7149d1f49738f9f01232cdcb610caca0e5f7e5d..34aca9ed0432afa8e855af5aecf6caa3ec1dd0e1 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -247,21 +247,25 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) /* Nonzero if this chip supports ldrex and strex */ -#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) +#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ + || arm_arch7 \ + || (arm_arch8 && !arm_arch_notm)) /* Nonzero if this chip supports LPAE. */ #define TARGET_HAVE_LPAE \ (arm_arch7 && ARM_FSET_HAS_CPU1 (insn_flags, FL_FOR_ARCH7VE)) /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ -#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) +#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ + || arm_arch7 \ + || (arm_arch8 && !arm_arch_notm)) /* Nonzero if this chip supports ldrexd and strexd. */ #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ || arm_arch7) && arm_arch_notm) /* Nonzero if this chip supports load-acquire and store-release. */ -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT) +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) /* Nonzero if this chip supports LDAEXD and STLEXD. */ #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ diff --git a/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c new file mode 100644 index 0000000000000000000000000000000000000000..0191f7af3a4656cb21c79c0f853f9e5a8aa44e86 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2 -fno-ipa-icf" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-comp-swap-release-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex" 4 } } */ +/* { dg-final { scan-assembler-times "stlex" 4 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c new file mode 100644 index 0000000000000000000000000000000000000000..f2ed32d01977466bd0afac013e8490beaf2a3691 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-acq_rel.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c new file mode 100644 index 0000000000000000000000000000000000000000..bba1c2709e74fd220275f35bda858aa805f8d080 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-acquire.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-char-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-char-3.c new file mode 100644 index 0000000000000000000000000000000000000000..17117eebf70b99ca2651520366563dc7043b9ddf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-char-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-char.x" + +/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c new file mode 100644 index 0000000000000000000000000000000000000000..8352f0c3af81c9ad25d7c9cda7e92fdd0e3ba0fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-consume.x" + +/* Scan for ldaex is a PR59448 consume workaround. */ +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-int-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-int-3.c new file mode 100644 index 0000000000000000000000000000000000000000..d4f1db34a1f1851b5d3bfa277ff106bb24e25f73 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-int-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-int.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c new file mode 100644 index 0000000000000000000000000000000000000000..09b5ea9f6d3bf0c324ee532ccae002d41b687105 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-relaxed.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-release-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-release-3.c new file mode 100644 index 0000000000000000000000000000000000000000..2b136f5ca2e7881cba218fa4980684f2ed082d30 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-release-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-release.x" + +/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c new file mode 100644 index 0000000000000000000000000000000000000000..7f38d42fa630819080171deee98fbc287e6957fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-seq_cst.x" + +/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */ diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-short-3.c b/gcc/testsuite/gcc.target/arm/atomic-op-short-3.c new file mode 100644 index 0000000000000000000000000000000000000000..60ae42ebc34802391761d2e6cd286bbe475b646b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/atomic-op-short-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8m_base_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8m_base } */ + +#include "../aarch64/atomic-op-short.x" + +/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */ +/* { dg-final { scan-assembler-not "dmb" } } */