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Sun, 31 Mar 2024 09:53:52 -0700 (PDT) Received: from [172.31.0.109] ([136.36.72.243]) by smtp.gmail.com with ESMTPSA id w22-20020a1709026f1600b001e0b5f9fb02sm7206433plk.26.2024.03.31.09.53.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 Mar 2024 09:53:52 -0700 (PDT) Message-ID: <1df2a508-1116-4d5f-b77a-91649cecc770@ventanamicro.com> Date: Sun, 31 Mar 2024 10:53:46 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Beta Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Cc: Chen Jiawei From: Jeff Law Subject: [committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler model X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org The test for the recently added XiangShan Nanhu microarchitecture is failing because the scheduler description does not have entries for certain insn types. I'm adding branch, jalr, ret and sfb_alu to the scheduler description, that's enough to get the trivial test to pass. However, I strongly suspect running any significant code through the compiler when scheduling for this microarchitecture will trigger faults. Basically we have checking now that will fault if we have an insn in the IL without an associated type or if we have an insn in the IL that does not map to an insn reservation in the scheduler model. We were tripping the latter assertion for one of those branch types. My suspicion is many insn types aren't handled by that DFA. The branch insns were pretty obvious and easy to fix. But someone with more experience with the uarch needs to do an audit to ensure that all insn types map to an insn reservation. Pushing this to the trunk. Jeff commit 08eaafadd5beaa56beb2d1fceca9f97eeb0219ba Author: Jeff Law Date: Sun Mar 31 10:51:17 2024 -0600 [committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler model The test for the recently added XiangShan Nanhu microarchitecture is failing because the scheduler description does not have entries for certain insn types. I'm adding branch, jalr, ret and sfb_alu to the scheduler description, that's enough to get the trivial test to pass. However, I strongly suspect running any significant code through the compiler when scheduling for this microarchitecture will trigger faults. Basically we have checking now that will fault if we have an insn in the IL without an associated type or if we have an insn in the IL that does not map to an insn reservation in the scheduler model. We were tripping the latter assertion for one of those branch types. My suspicion is many insn types aren't handled by that DFA. The branch insns were pretty obvious and easy to fix. But someone with more experience with the uarch needs to do an audit to ensure that all insn types map to an insn reservation. gcc/ * config/riscv/xiangshan.md (xiangshan_jump): Add branch, jalr, ret and sfb_alu. diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md index 381c3ce1428..76539d332b8 100644 --- a/gcc/config/riscv/xiangshan.md +++ b/gcc/config/riscv/xiangshan.md @@ -70,7 +70,7 @@ (define_insn_reservation "xiangshan_fpstore" 1 (define_insn_reservation "xiangshan_jump" 1 (and (eq_attr "tune" "xiangshan") - (eq_attr "type" "jump,call,auipc,unknown")) + (eq_attr "type" "jump,call,auipc,unknown,branch,jalr,ret,sfb_alu")) "xs_jmp_rs") (define_insn_reservation "xiangshan_i2f" 3