| Message ID | 1df2a508-1116-4d5f-b77a-91649cecc770@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | [committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler model | expand |
On Sun, 31 Mar 2024 09:53:46 PDT (-0700), Jeff Law wrote: > The test for the recently added XiangShan Nanhu microarchitecture is > failing because the scheduler description does not have entries for > certain insn types. > > I'm adding branch, jalr, ret and sfb_alu to the scheduler description, > that's enough to get the trivial test to pass. However, I strongly > suspect running any significant code through the compiler when > scheduling for this microarchitecture will trigger faults. We should probably add a build with this a the default pipeline model to the lists of tests, even if it's just something we run every few weeks it'd still be good. > Basically we have checking now that will fault if we have an insn in the > IL without an associated type or if we have an insn in the IL that does > not map to an insn reservation in the scheduler model. We were tripping > the latter assertion for one of those branch types. My suspicion is > many insn types aren't handled by that DFA. > > The branch insns were pretty obvious and easy to fix. But someone with > more experience with the uarch needs to do an audit to ensure that all > insn types map to an insn reservation. > > Pushing this to the trunk. > > Jeff > > > > commit 08eaafadd5beaa56beb2d1fceca9f97eeb0219ba > Author: Jeff Law <jlaw@ventanamicro.com> > Date: Sun Mar 31 10:51:17 2024 -0600 > > [committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler model > > The test for the recently added XiangShan Nanhu microarchitecture is failing > because the scheduler description does not have entries for certain insn types. > > I'm adding branch, jalr, ret and sfb_alu to the scheduler description, that's > enough to get the trivial test to pass. However, I strongly suspect running > any significant code through the compiler when scheduling for this > microarchitecture will trigger faults. > > Basically we have checking now that will fault if we have an insn in the IL > without an associated type or if we have an insn in the IL that does not map to > an insn reservation in the scheduler model. We were tripping the latter > assertion for one of those branch types. My suspicion is many insn types > aren't handled by that DFA. > > The branch insns were pretty obvious and easy to fix. But someone with more > experience with the uarch needs to do an audit to ensure that all insn types > map to an insn reservation. > > gcc/ > * config/riscv/xiangshan.md (xiangshan_jump): Add branch, jalr, ret > and sfb_alu. > > diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md > index 381c3ce1428..76539d332b8 100644 > --- a/gcc/config/riscv/xiangshan.md > +++ b/gcc/config/riscv/xiangshan.md > @@ -70,7 +70,7 @@ (define_insn_reservation "xiangshan_fpstore" 1 > > (define_insn_reservation "xiangshan_jump" 1 > (and (eq_attr "tune" "xiangshan") > - (eq_attr "type" "jump,call,auipc,unknown")) > + (eq_attr "type" "jump,call,auipc,unknown,branch,jalr,ret,sfb_alu")) > "xs_jmp_rs") > > (define_insn_reservation "xiangshan_i2f" 3
diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md index 381c3ce1428..76539d332b8 100644 --- a/gcc/config/riscv/xiangshan.md +++ b/gcc/config/riscv/xiangshan.md @@ -70,7 +70,7 @@ (define_insn_reservation "xiangshan_fpstore" 1 (define_insn_reservation "xiangshan_jump" 1 (and (eq_attr "tune" "xiangshan") - (eq_attr "type" "jump,call,auipc,unknown")) + (eq_attr "type" "jump,call,auipc,unknown,branch,jalr,ret,sfb_alu")) "xs_jmp_rs") (define_insn_reservation "xiangshan_i2f" 3
The test for the recently added XiangShan Nanhu microarchitecture is failing because the scheduler description does not have entries for certain insn types. I'm adding branch, jalr, ret and sfb_alu to the scheduler description, that's enough to get the trivial test to pass. However, I strongly suspect running any significant code through the compiler when scheduling for this microarchitecture will trigger faults. Basically we have checking now that will fault if we have an insn in the IL without an associated type or if we have an insn in the IL that does not map to an insn reservation in the scheduler model. We were tripping the latter assertion for one of those branch types. My suspicion is many insn types aren't handled by that DFA. The branch insns were pretty obvious and easy to fix. But someone with more experience with the uarch needs to do an audit to ensure that all insn types map to an insn reservation. Pushing this to the trunk. Jeff commit 08eaafadd5beaa56beb2d1fceca9f97eeb0219ba Author: Jeff Law <jlaw@ventanamicro.com> Date: Sun Mar 31 10:51:17 2024 -0600 [committed] RISC-V: Add missing insn types to XiangShan Nanhu scheduler model The test for the recently added XiangShan Nanhu microarchitecture is failing because the scheduler description does not have entries for certain insn types. I'm adding branch, jalr, ret and sfb_alu to the scheduler description, that's enough to get the trivial test to pass. However, I strongly suspect running any significant code through the compiler when scheduling for this microarchitecture will trigger faults. Basically we have checking now that will fault if we have an insn in the IL without an associated type or if we have an insn in the IL that does not map to an insn reservation in the scheduler model. We were tripping the latter assertion for one of those branch types. My suspicion is many insn types aren't handled by that DFA. The branch insns were pretty obvious and easy to fix. But someone with more experience with the uarch needs to do an audit to ensure that all insn types map to an insn reservation. gcc/ * config/riscv/xiangshan.md (xiangshan_jump): Add branch, jalr, ret and sfb_alu.