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Wed, 19 Jun 2024 12:39:29 +0000 (GMT) Message-ID: <18dfc483-0815-4ede-aa20-0833a83d9671@linux.ibm.com> Date: Wed, 19 Jun 2024 18:09:28 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH V2] rs6000: load high and low part of 128bit vector independently [PR110040] References: <1a62a215-98e2-4e3b-9059-681189157d0a@linux.vnet.ibm.com> Content-Language: en-US From: jeevitha To: "Kewen.Lin" , GCC Patches , Segher Boessenkool , Peter Bergner In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: D_g0wu2lj7unz5vpap7pGLfLqFBzh2On X-Proofpoint-GUID: D_g0wu2lj7unz5vpap7pGLfLqFBzh2On X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-19_02,2024-06-19_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406190092 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi All, Updated the patch based on review comments. This patch passed bootstrap and regression testing on powerpc64le-linux with no regressions. PR110040 exposes an issue concerning moves from vector registers to GPRs. There are two moves, one for upper 64 bits and the other for the lower 64 bits. In the problematic test case, we are only interested in storing the lower 64 bits. However, the instruction for copying the upper 64 bits is still emitted and is dead code. This patch adds a splitter that splits apart the two move instructions so that DCE can remove the dead code after splitting. 2024-06-19 Jeevitha Palanisamy gcc/ PR target/110040 * config/rs6000/vsx.md (split pattern for V1TI to DI move): Defined. gcc/testsuite/ PR target/110040 * gcc.target/powerpc/pr110040-1.c: New testcase. * gcc.target/powerpc/pr110040-2.c: New testcase. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f135fa079bd..f1979815df6 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -6706,3 +6706,20 @@ "vmsumcud %0,%1,%2,%3" [(set_attr "type" "veccomplex")] ) + +(define_split + [(set (match_operand:V1TI 0 "gpc_reg_operand") + (match_operand:V1TI 1 "vsx_register_operand"))] + "reload_completed + && TARGET_DIRECT_MOVE_64BIT + && int_reg_operand (operands[0], V1TImode) + && vsx_register_operand (operands[1], V1TImode)" + [(pc)] +{ + rtx src_op = gen_rtx_REG (V2DImode, REGNO (operands[1])); + rtx dest_op0 = gen_rtx_REG (DImode, REGNO (operands[0])); + rtx dest_op1 = gen_rtx_REG (DImode, REGNO (operands[0]) + 1); + emit_insn (gen_vsx_extract_v2di (dest_op0, src_op, const0_rtx)); + emit_insn (gen_vsx_extract_v2di (dest_op1, src_op, const1_rtx)); + DONE; +}) diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-1.c b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c new file mode 100644 index 00000000000..0a521e9e51d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c @@ -0,0 +1,15 @@ +/* PR target/110040 */ +/* { dg-do compile } */ +/* { dg-require-effective-target int128 } */ +/* { dg-require-effective-target powerpc_vsx } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ + +#include + +void +foo (signed long *dst, vector signed __int128 src) +{ + *dst = (signed long) src[0]; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-2.c b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c new file mode 100644 index 00000000000..d2ef471d666 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c @@ -0,0 +1,16 @@ +/* PR target/110040 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ +/* { dg-require-effective-target int128 } */ +/* { dg-require-effective-target powerpc_vsx } */ +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ + +/* Note: __builtin_altivec_tr_stxvrwx requires the -mcpu=power10 option */ + +#include + +void +foo (signed int *dst, vector signed __int128 src) +{ + __builtin_vec_xst_trunc (src, 0, dst); +}