From patchwork Tue May 17 10:15:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 622996 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r8Cs84wBDz9t6B for ; Tue, 17 May 2016 20:15:56 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=wAywUYhn; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; q=dns; s= default; b=O81YxFbkiUcXiR0yF/fD2mdYnPJ3WMW67BLbpLgaiIqESYP/UFist gjxzep7vc5KctoadXHBR7DucRnnuZxkhkfSZHo83TD5gq2ViBtMI4QnwfCfuo1iP xKifFieMBb/VJcwEMMRBXWOebjouU3NdN0Qh7da5j7PsT5UWlpytYE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=default; bh=h1BZ8qWbGoyqWEnZ0dRMztpbyWs=; b=wAywUYhndAKnWRlA4s5devqniUmi Oha/mn2Sx5dC6+SSfbO1/7SSg9ccndt5tYgW/l380z2MwR4YGbNDEjqhy8JOR0ON IvsAbviaQT7HACAKagSEaxbMx3gR1lO17T8c+jy07O2UI7H1hm73mA38ZUHqAtOY QXUegZ6BvkXn4q8= Received: (qmail 51061 invoked by alias); 17 May 2016 10:15:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 51031 invoked by uid 89); 17 May 2016 10:15:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=20151217, 2015-12-17, HContent-Transfer-Encoding:7Bit, letter X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 17 May 2016 10:15:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 635E329; Tue, 17 May 2016 03:15:44 -0700 (PDT) Received: from e108577-lin.localnet (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 36FA63F21A; Tue, 17 May 2016 03:15:27 -0700 (PDT) From: Thomas Preudhomme To: Richard Earnshaw , Ramana Radhakrishnan , Kyrylo Tkachov Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH, ARM 7/7, ping1] Enable atomics for ARMv8-M Mainline Date: Tue, 17 May 2016 11:15:25 +0100 Message-ID: <1605324.7ye6nFaIcv@e108577-lin> User-Agent: KMail/4.13.3 (Linux/3.13.0-85-generic; KDE/4.13.3; x86_64; ; ) In-Reply-To: <006a01d138ae$d5014430$7f03cc90$@foss.arm.com> References: <006a01d138ae$d5014430$7f03cc90$@foss.arm.com> MIME-Version: 1.0 X-IsSubscribed: yes Ping? *** gcc/ChangeLog *** 2015-12-17 Thomas Preud'homme * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline. #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) Best regards, Thomas On Thursday 17 December 2015 17:39:29 Thomas Preud'homme wrote: > Hi, > > This patch is part of a patch series to add support for ARMv8-M[1] to GCC. > This specific patch enable atomics for ARMv8-M Mainline. No change is > needed to existing patterns since Thumb-2 backend can already handle them > fine. > > [1] For a quick overview of ARMv8-M please refer to the initial cover > letter. > > > ChangeLog entries are as follow: > > *** gcc/ChangeLog *** > > 2015-12-17 Thomas Preud'homme > > * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline. > > > diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h > index > 1f79c37b5c36a410a2d500ba92c62a5ba4ca1178..fa2a6fb03ffd2ca53bfb7e7c8f03022b6 > 26880e0 100644 --- a/gcc/config/arm/arm.h > +++ b/gcc/config/arm/arm.h > @@ -258,7 +258,7 @@ extern void > (*arm_lang_output_object_attributes_hook)(void); > || arm_arch7) && arm_arch_notm) > > /* Nonzero if this chip supports load-acquire and store-release. */ > -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm) > +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT) > > /* Nonzero if this chip provides the movw and movt instructions. */ > #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) > > > Testing: > > * Toolchain was built successfully with and without the ARMv8-M support > patches with the following multilib list: > armv6-m,armv7-m,armv7e-m,cortex-m7. The code generation for crtbegin.o, > crtend.o, crti.o, crtn.o, libgcc.a, libgcov.a, libc.a, libg.a, > libgloss-linux.a, libm.a, libnosys.a, librdimon.a, librdpmon.a, libstdc++.a > and libsupc++.a is unchanged for all these targets. > > * GCC also showed no testsuite regression when targeting ARMv8-M Baseline > compared to ARMv6-M on ARM Fast Models and when targeting ARMv6-M and > ARMv7-M (compared to without the patch) * GCC was bootstrapped successfully > targeting Thumb-1 and targeting Thumb-2 > > Is this ok for stage3? > > Best regards, > > Thomas diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 347b5b0a5cc0bc1e3b5020c8124d968e76ce48a4..e154bd31b8084f9f45ad4409e7b38de652538c51 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -266,7 +266,7 @@ extern void (*arm_lang_output_object_attributes_hook) (void); || arm_arch7) && arm_arch_notm) /* Nonzero if this chip supports load-acquire and store-release. */ -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm) +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT) /* Nonzero if this chip provides the movw and movt instructions. */