Message ID | 1605324.7ye6nFaIcv@e108577-lin |
---|---|
State | New |
Headers | show |
Hi Thomas, On 17/05/16 11:15, Thomas Preudhomme wrote: > Ping? > > *** gcc/ChangeLog *** > > 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com> > > * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline. > > > diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h > index > 347b5b0a5cc0bc1e3b5020c8124d968e76ce48a4..e154bd31b8084f9f45ad4409e7b38de652538c51 > 100644 > --- a/gcc/config/arm/arm.h > +++ b/gcc/config/arm/arm.h > @@ -266,7 +266,7 @@ extern void (*arm_lang_output_object_attributes_hook) > (void); > || arm_arch7) && arm_arch_notm) > > /* Nonzero if this chip supports load-acquire and store-release. */ > -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm) > +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT) > So this change is correct because ARMv8-M Mainline uses Thumb2 and is therefore TARGET_32BIT. This is ok but I'd like to see a follow up patch to enable the tests that exercise acquire-release instructions in the arm.exp testsuite for ARMv8-M Mainline so that we can be sure they get proper testsuite coverage. Thanks, Kyrill > /* Nonzero if this chip provides the movw and movt instructions. */ > #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) > > > Best regards, > > Thomas > > On Thursday 17 December 2015 17:39:29 Thomas Preud'homme wrote: >> Hi, >> >> This patch is part of a patch series to add support for ARMv8-M[1] to GCC. >> This specific patch enable atomics for ARMv8-M Mainline. No change is >> needed to existing patterns since Thumb-2 backend can already handle them >> fine. >> >> [1] For a quick overview of ARMv8-M please refer to the initial cover >> letter. >> >> >> ChangeLog entries are as follow: >> >> *** gcc/ChangeLog *** >> >> 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com> >> >> * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline. >> >> >> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h >> index >> 1f79c37b5c36a410a2d500ba92c62a5ba4ca1178..fa2a6fb03ffd2ca53bfb7e7c8f03022b6 >> 26880e0 100644 --- a/gcc/config/arm/arm.h >> +++ b/gcc/config/arm/arm.h >> @@ -258,7 +258,7 @@ extern void >> (*arm_lang_output_object_attributes_hook)(void); >> || arm_arch7) && arm_arch_notm) >> >> /* Nonzero if this chip supports load-acquire and store-release. */ >> -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm) >> +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT) >> >> /* Nonzero if this chip provides the movw and movt instructions. */ >> #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) >> >> >> Testing: >> >> * Toolchain was built successfully with and without the ARMv8-M support >> patches with the following multilib list: >> armv6-m,armv7-m,armv7e-m,cortex-m7. The code generation for crtbegin.o, >> crtend.o, crti.o, crtn.o, libgcc.a, libgcov.a, libc.a, libg.a, >> libgloss-linux.a, libm.a, libnosys.a, librdimon.a, librdpmon.a, libstdc++.a >> and libsupc++.a is unchanged for all these targets. >> >> * GCC also showed no testsuite regression when targeting ARMv8-M Baseline >> compared to ARMv6-M on ARM Fast Models and when targeting ARMv6-M and >> ARMv7-M (compared to without the patch) * GCC was bootstrapped successfully >> targeting Thumb-1 and targeting Thumb-2 >> >> Is this ok for stage3? >> >> Best regards, >> >> Thomas
On Thursday 19 May 2016 17:18:29 Kyrill Tkachov wrote: > Hi Thomas, > > On 17/05/16 11:15, Thomas Preudhomme wrote: > > Ping? > > > > *** gcc/ChangeLog *** > > > > 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com> > > > > * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M > > Mainline. > > > > diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h > > index > > 347b5b0a5cc0bc1e3b5020c8124d968e76ce48a4..e154bd31b8084f9f45ad4409e7b38de6 > > 52538c51 100644 > > --- a/gcc/config/arm/arm.h > > +++ b/gcc/config/arm/arm.h > > @@ -266,7 +266,7 @@ extern void (*arm_lang_output_object_attributes_hook) > > (void); > > > > || arm_arch7) && arm_arch_notm) > > > > /* Nonzero if this chip supports load-acquire and store-release. */ > > > > -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm) > > +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT) > > So this change is correct because ARMv8-M Mainline uses Thumb2 > and is therefore TARGET_32BIT. > > This is ok but I'd like to see a follow up patch to enable the tests > that exercise acquire-release instructions in the arm.exp testsuite > for ARMv8-M Mainline so that we can be sure they get proper testsuite > coverage. Good thing I already have one around. I need to separate it from other stuff though, so I'll probably send it on Monday. Cheers, Thomas
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 347b5b0a5cc0bc1e3b5020c8124d968e76ce48a4..e154bd31b8084f9f45ad4409e7b38de652538c51 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -266,7 +266,7 @@ extern void (*arm_lang_output_object_attributes_hook) (void); || arm_arch7) && arm_arch_notm) /* Nonzero if this chip supports load-acquire and store-release. */ -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm) +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT) /* Nonzero if this chip provides the movw and movt instructions. */