From patchwork Thu Nov 8 17:54:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Steve Ellcey X-Patchwork-Id: 995083 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-489439-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=cavium.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="RjW6nmeG"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com header.i=@CAVIUMNETWORKS.onmicrosoft.com header.b="YSWti7DS"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42rWC46CrRz9s55 for ; Fri, 9 Nov 2018 04:54:56 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:content-type:mime-version:reply-to; q=dns; s=default; b=XifxQoMI3+73BQCMs6VJLrkqCUQkNQum5O8nuDgYoCn HYFCrCMAbwKASXTMH6YAblS8MFQy7bLGwOea4TsIWQam4GDCjy4j1kVfTyyUmxMy uZqCgQFqqRvgGhmAKa9R+1thH+8BJfpdizqK11BTSsdQ5m0hGwS2KWpXvxJp5osY = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:content-type:mime-version:reply-to; s=default; bh=zX+jSFxv/2ZIoOzx6Hq/blaMIJ0=; b=RjW6nmeGcnRgESF7d gQaRI+wtbNcXosg6njCLuRMd8vSRID9x+wUmVxA+jr3h8+qptzYp4EWccVzboG2T GY5qlarpENKQHUKoe8lhwFaZBOJ+P/Uh30WDmpDfBMdiFzuGOkHysOn7PCDX0YrK VdQr/uzxCdmN3OJRMRC1D0evVw= Received: (qmail 68875 invoked by alias); 8 Nov 2018 17:54:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 68861 invoked by uid 89); 8 Nov 2018 17:54:49 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: NAM01-BN3-obe.outbound.protection.outlook.com Received: from mail-eopbgr740070.outbound.protection.outlook.com (HELO NAM01-BN3-obe.outbound.protection.outlook.com) (40.107.74.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 08 Nov 2018 17:54:46 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0BKUDXmgTILxqkxZYSlqEKyjgXz+ccHsfnfTQcxptd8=; b=YSWti7DSvj7w0ishTPNeTgVcbzEhv9svGa8xCGRrq4gc7BRojEM6ztJ3UHVpj0FNCvDjLzmgiJVOIplaqOsk+tytHDE985uLGTAf701rcPbU0AQNJZxgdXRWrtgPGPkqijC61iujczmOK9xP+d4I1B/nkpx3UFf1m1ifZ/O6hfU= Received: from BYAPR07MB5031.namprd07.prod.outlook.com (52.135.238.224) by BYAPR07MB5157.namprd07.prod.outlook.com (20.176.254.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1294.32; Thu, 8 Nov 2018 17:54:44 +0000 Received: from BYAPR07MB5031.namprd07.prod.outlook.com ([fe80::50ef:7350:fb0f:1d41]) by BYAPR07MB5031.namprd07.prod.outlook.com ([fe80::50ef:7350:fb0f:1d41%4]) with mapi id 15.20.1294.034; Thu, 8 Nov 2018 17:54:44 +0000 From: Steve Ellcey To: gcc-patches Subject: [Patch 3/4][Aarch64] v2: Implement Aarch64 SIMD ABI Date: Thu, 8 Nov 2018 17:54:44 +0000 Message-ID: <1541699683.12016.8.camel@cavium.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Steve.Ellcey@cavium.com; received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) MIME-Version: 1.0 Reply-To: This is a patch 3 to support the Aarch64 SIMD ABI [1] in GCC. It defines a new target hook targetm.remove_extra_call_preserved_regs that takes a rtx_insn and will remove registers from the register set passed in if we know that this call preserves those registers. Aarch64 SIMD functions preserve some registers that normal functions do not.  The default version of this function will do nothing. Steve Ellcey sellcey@cavium.com 2018-11-08  Steve Ellcey   * config/aarch64/aarch64.c (aarch64_simd_call_p): New function. (aarch64_remove_extra_call_preserved_regs): New function. (TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS): New macro. * doc/tm.texi.in (TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS): New hook. * final.c (get_call_reg_set_usage): Call new hook. * target.def (remove_extra_call_preserved_regs): New hook. * targhooks.c (default_remove_extra_call_preserved_regs): New function. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index c82c7b6..62112ac 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1470,6 +1470,50 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode) return false; } +/* Return true if the instruction is a call to a SIMD function, false + if it is not a SIMD function or if we do not know anything about + the function. */ + +static bool +aarch64_simd_call_p (rtx_insn *insn) +{ + rtx symbol; + rtx call; + tree fndecl; + + if (!insn) + return false; + call = get_call_rtx_from (insn); + if (!call) + return false; + symbol = XEXP (XEXP (call, 0), 0); + if (GET_CODE (symbol) != SYMBOL_REF) + return false; + fndecl = SYMBOL_REF_DECL (symbol); + if (!fndecl) + return false; + + return aarch64_simd_decl_p (fndecl); +} + +/* Possibly remove some registers from register set if we know they + are preserved by this call, even though they are marked as not + being callee saved in CALL_USED_REGISTERS. */ + +void +aarch64_remove_extra_call_preserved_regs (rtx_insn *insn, + HARD_REG_SET *return_set) +{ + int regno; + + if (aarch64_simd_call_p (insn)) + { + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (FP_SIMD_SAVED_REGNUM_P (regno)) + CLEAR_HARD_REG_BIT (*return_set, regno); + } +} + /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves the lower 64 bits of a 128-bit register. Tell the compiler the callee clobbers the top 64 bits when restoring the bottom 64 bits. */ @@ -18290,6 +18334,10 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_MODES_TIEABLE_P #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p +#undef TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS +#define TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS \ + aarch64_remove_extra_call_preserved_regs + #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \ aarch64_hard_regno_call_part_clobbered diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index e8af1bf..73febe9 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -1704,6 +1704,8 @@ of @code{CALL_USED_REGISTERS}. @cindex call-saved register @hook TARGET_HARD_REGNO_CALL_PART_CLOBBERED +@hook TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS + @findex fixed_regs @findex call_used_regs @findex global_regs diff --git a/gcc/final.c b/gcc/final.c index 6e61f1e..8df869e 100644 --- a/gcc/final.c +++ b/gcc/final.c @@ -5080,7 +5080,7 @@ get_call_reg_set_usage (rtx_insn *insn, HARD_REG_SET *reg_set, return true; } } - COPY_HARD_REG_SET (*reg_set, default_set); + targetm.remove_extra_call_preserved_regs (insn, reg_set); return false; } diff --git a/gcc/target.def b/gcc/target.def index 4b166d1..25be927 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -5757,6 +5757,12 @@ for targets that don't have partly call-clobbered registers.", bool, (unsigned int regno, machine_mode mode), hook_bool_uint_mode_false) +DEFHOOK +(remove_extra_call_preserved_regs, + "This hook removes some registers from the callee used register set.", + void, (rtx_insn *insn, HARD_REG_SET *used_regs), + default_remove_extra_call_preserved_regs) + /* Return the smallest number of different values for which it is best to use a jump-table instead of a tree of conditional branches. */ DEFHOOK diff --git a/gcc/targhooks.c b/gcc/targhooks.c index 3d8b3b9..a9fb101 100644 --- a/gcc/targhooks.c +++ b/gcc/targhooks.c @@ -2372,4 +2372,11 @@ default_speculation_safe_value (machine_mode mode ATTRIBUTE_UNUSED, return result; } +void +default_remove_extra_call_preserved_regs (rtx_insn *insn ATTRIBUTE_UNUSED, + HARD_REG_SET *used_regs + ATTRIBUTE_UNUSED) +{ +} + #include "gt-targhooks.h"