new file mode 100644
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_sel with char
+ inputs produce the right code. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector bool char
+test1_0 (vector bool char x, vector bool char y, vector bool char z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector bool char
+test1_1 (vector bool char x,vector bool char y, vector unsigned char z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector signed char
+test3_0 (vector signed char x,vector signed char y, vector bool char z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector signed char
+test3_1 (vector signed char x,vector signed char y, vector unsigned char z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector unsigned char
+test6_0 (vector unsigned char x,vector unsigned char y,vector bool char z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector unsigned char
+test6_1 (vector unsigned char x,vector unsigned char y, vector unsigned char z)
+{
+ return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 6 } } */
new file mode 100644
@@ -0,0 +1,22 @@
+/* Verify that overloaded built-ins for vec_sel with
+ double inputs for VSX produce the right code. */
+
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mvsx -mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector double
+test2_0 (vector double x, vector double y, vector bool long long z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector double
+test2_1 (vector double x, vector double y, vector unsigned long z)
+{
+ return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times "xxsel" 2 } } */
new file mode 100644
@@ -0,0 +1,22 @@
+/* Verify that overloaded built-ins for vec_sel with float
+ inputs for VSX produce the right code. */
+
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector float
+test1_0 (vector float x, vector float y, vector bool int z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector float
+test1_1 (vector float x, vector float y, vector unsigned int z)
+{
+ return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 2 } } */
new file mode 100644
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_sel with int
+ inputs produce the right code. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector bool int
+test1_0 (vector bool int x, vector bool int y, vector bool int z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector bool int
+test1_1 (vector bool int x, vector bool int y, vector unsigned int z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector signed int
+test3_0 (vector signed int x, vector signed int y, vector bool int z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector signed int
+test3_1 (vector signed int x, vector signed int y, vector unsigned int z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector unsigned int
+test6_0 (vector unsigned int x, vector unsigned int y, vector bool int z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector unsigned int
+test6_1 (vector unsigned int x, vector unsigned int y, vector unsigned int z)
+{
+ return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 6 } } */
new file mode 100644
@@ -0,0 +1,34 @@
+/* Verify that overloaded built-ins for vec_sel with long long
+ inputs produce the right code. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+#include <altivec.h>
+
+vector bool long long
+test1_0 (vector bool long long x,vector bool long long y, vector bool long long z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector bool long long
+test1_1 (vector bool long long x, vector bool long long y, vector unsigned long long z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector signed long long
+test3_0 (vector signed long long x, vector signed long long y, vector bool long long z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector unsigned long long
+test3_1 (vector unsigned long long x, vector unsigned long long y, vector bool long long z)
+{
+ return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times "xxsel" 4 } } */
new file mode 100644
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_sel with short
+ inputs produce the right code. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector bool short
+test1_0 (vector bool short x, vector bool short y, vector bool short z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector bool short
+test1_1 (vector bool short x, vector bool short y, vector unsigned short z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector signed short
+test3_0 (vector signed short x, vector signed short y, vector bool short z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector signed short
+test3_1 (vector signed short x, vector signed short y, vector unsigned short z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector unsigned short
+test6_0 (vector unsigned short x, vector unsigned short y, vector bool short z)
+{
+ return vec_sel (x, y, z);
+}
+
+vector unsigned short
+test6_1 (vector unsigned short x, vector unsigned short y, vector unsigned short z)
+{
+ return vec_sel (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times {\mxxsel\M|\mvsel\M} 6 } } */