diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-13.c b/gcc/testsuite/gcc.target/powerpc/altivec-13.c
index 2315f6e..31ff509 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-13.c
@@ -6,54 +6,47 @@
 
 /* This test case exercises intrinsic/argument combinations that,
    while not in the Motorola AltiVec PIM, have nevertheless crept
    into the AltiVec vernacular over the years.  */
 
+/* Tests requiring VSX support (vector long long and vector double) have
+   been moved over to vsx-13.c.  */
+
 #include <altivec.h>
 
-void foo (void) 
+void foo (void)
 {
   vector bool int boolVec1 = (vector bool int) vec_splat_u32(3);
   vector bool short boolVec2 = (vector bool short) vec_splat_u16(3);
   vector bool char boolVec3 = (vector bool char) vec_splat_u8(3);
   vector signed char vsc1, vsc2, vscz;
   vector unsigned char vuc1, vuc2, vucz;
   vector signed short int vssi1, vssi2, vssiz;
   vector signed int vsi1, vsi2, vsiz;
   vector unsigned int vui1, vui2, vuiz;
   vector unsigned short int vusi1, vusi2, vusiz;
-  vector bool long long vubll1, vubll2, vubllz;
-  vector signed int long long vsill1, vsill2, vsillz;
-  vector unsigned int long long vuill1, vuill2, vuillz;
   vector pixel vp1, vp2, vpz;
   vector float vf1, vf2, vfz;
-  vector double vd1, vd2, vdz;
   
   boolVec1 = vec_sld( boolVec1, boolVec1, 4 );
   boolVec2 = vec_sld( boolVec2, boolVec2, 2 );
   boolVec3 = vec_sld( boolVec3, boolVec3, 1 );
 
   vscz = vec_sld( vsc1, vsc2, 1 );
   vucz = vec_sld( vuc1, vuc2, 1 );
   vsiz = vec_sld( vsi1, vsi2, 1 );
   vuiz = vec_sld( vui1, vui2, 1 );
-  vubllz = vec_sld( vubll1, vubll2, 1 );
-  vsillz = vec_sld( vsill1, vsill2, 1 );
-  vuillz = vec_sld( vuill1, vuill2, 1 );
   vssiz = vec_sld( vssi1, vssi2, 1 );
   vusiz = vec_sld( vusi1, vusi2, 1 );
   
   vfz = vec_sld( vf1, vf2, 1 );
-  vdz = vec_sld( vd1, vd2, 1 );
 
   vpz = vec_sld( vp1, vp2, 1 );
 
   vucz = vec_srl(vuc1, vuc2);
   vsiz = vec_srl(vsi1, vuc2);
   vuiz = vec_srl(vui1, vuc2);
-  vsillz = vec_srl(vsill1, vuc2);
-  vuillz = vec_srl(vuill1, vuc2);
   vpz = vec_srl(vp1, vuc2);
   vssiz = vec_srl(vssi1, vuc2);
   vusiz = vec_srl(vusi1, vuc2);
 
   vscz = vec_sro(vsc1, vsc2);
@@ -62,14 +55,10 @@ void foo (void)
   vucz = vec_sro(vuc1, vuc2);
   vsiz = vec_sro(vsi1, vsc2);
   vsiz = vec_sro(vsi1, vuc2);
   vuiz = vec_sro(vui1, vsc2);
   vuiz = vec_sro(vui1, vuc2);
-  vsillz = vec_sro(vsill1, vsc2);
-  vsillz = vec_sro(vsill1, vuc2);
-  vuillz = vec_sro(vuill1, vsc2);
-  vuillz = vec_sro(vuill1, vuc2);
   vpz = vec_sro(vp1, vsc2);
   vpz = vec_sro(vp1, vuc2);
   vssiz = vec_sro(vssi1, vsc2);
   vssiz = vec_sro(vssi1, vuc2);
   vusiz = vec_sro(vusi1, vsc2);
@@ -81,8 +70,8 @@ void foo (void)
 /* Expected results:
    vec_sld          vsldoi
    vec_srl          vsr
    vec_sro          vsro  */
 
-/* { dg-final { scan-assembler-times "vsldoi" 15 } } */
-/* { dg-final { scan-assembler-times "vsr " 8 } } */
-/* { dg-final { scan-assembler-times "vsro" 20 } } */
+/* { dg-final { scan-assembler-times "vsldoi" 11 } } */
+/* { dg-final { scan-assembler-times "vsr " 6 } } */
+/* { dg-final { scan-assembler-times "vsro" 16 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-13.c b/gcc/testsuite/gcc.target/powerpc/vsx-13.c
new file mode 100644
index 0000000..5b4eb68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-13.c
@@ -0,0 +1,42 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx" } */
+
+/* Variations of tests that require VSX support.  This is a variation of
+   the altivec-13.c testcase.  */
+
+#include <altivec.h>
+
+void foo (void)
+{
+
+  vector signed char vsc1, vsc2, vscz;
+  vector unsigned char vuc1, vuc2, vucz;
+  vector bool long long vubll1, vubll2, vubllz;
+  vector signed int long long vsill1, vsill2, vsillz;
+  vector unsigned int long long vuill1, vuill2, vuillz;
+  vector double vd1, vd2, vdz;
+
+  vubllz = vec_sld( vubll1, vubll2, 1 );
+  vsillz = vec_sld( vsill1, vsill2, 1 );
+  vuillz = vec_sld( vuill1, vuill2, 1 );
+
+  vsillz = vec_srl(vsill1, vuc2);
+  vuillz = vec_srl(vuill1, vuc2);
+
+  vsillz = vec_sro(vsill1, vsc2);
+  vsillz = vec_sro(vsill1, vuc2);
+  vuillz = vec_sro(vuill1, vsc2);
+  vuillz = vec_sro(vuill1, vuc2);
+
+  vdz = vec_sld( vd1, vd2, 1 );
+}
+
+/* Expected results:
+   vec_sld          vsldoi
+   vec_srl          vsr
+   vec_sro          vsro  */
+
+/* { dg-final { scan-assembler-times "vsldoi" 4 } } */
+/* { dg-final { scan-assembler-times "vsr " 2 } } */
+/* { dg-final { scan-assembler-times "vsro" 4 } } */
