| Message ID | 1509108230-16347-1-git-send-email-siddhesh@gotplt.org |
|---|---|
| State | New |
| Headers | show |
| Series | New option saphira for Qualcomm server part | expand |
Ping! Siddhesh On 27 October 2017 at 18:13, Siddhesh Poyarekar <siddhesh@gotplt.org> wrote: > From: Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org> > > This patch adds an mcpu option for the Qualcomm saphira server part. > Tested on aarch64 and did not find any regressions resulting from this > patch. > > Siddhesh > > 2017-10-27 Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org> > Jim Wilson <jim.wilson@linaro.org> > > gcc/ > * config/aarch64/aarch64-cores.def (saphira): New. > * config/aarch64/aarch64-tune.md: Regenerated. > * doc/invoke.texi (AArch64 Options/-mtune): Add "saphira". > * gcc/config/aarch64/aarch64.c (saphira_tunings): New. > > Change-Id: I23c4a1ab74e4376c3800cb1481c508bc27418508 > --- > gcc/config/aarch64/aarch64-cores.def | 5 +++++ > gcc/config/aarch64/aarch64-tune.md | 2 +- > gcc/config/aarch64/aarch64.c | 28 ++++++++++++++++++++++++++++ > gcc/doc/invoke.texi | 2 +- > 4 files changed, 35 insertions(+), 2 deletions(-) > > diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def > index 16e4485..cdf047c 100644 > --- a/gcc/config/aarch64/aarch64-cores.def > +++ b/gcc/config/aarch64/aarch64-cores.def > @@ -86,6 +86,11 @@ AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR > AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1) > AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1) > > +/* ARMv8.3-A Architecture Processors. */ > + > +/* Qualcomm ('Q') cores. */ > +AARCH64_CORE("saphira", saphira, falkor, 8_3A, AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira, 0x51, 0xC01, -1) > + > /* ARMv8-A big.LITTLE implementations. */ > > AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1) > diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md > index 7fcd6cb..7b3a746 100644 > --- a/gcc/config/aarch64/aarch64-tune.md > +++ b/gcc/config/aarch64/aarch64-tune.md > @@ -1,5 +1,5 @@ > ;; -*- buffer-read-only: t -*- > ;; Generated automatically by gentune.sh from aarch64-cores.def > (define_attr "tune" > - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" > + "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" > (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > index d1aaf19..f554ffb 100644 > --- a/gcc/config/aarch64/aarch64.c > +++ b/gcc/config/aarch64/aarch64.c > @@ -822,6 +822,34 @@ static const struct tune_params qdf24xx_tunings = > &qdf24xx_prefetch_tune > }; > > +/* Tuning structure for the Qualcomm Saphira core. Default to falkor values > + for now. */ > +static const struct tune_params saphira_tunings = > +{ > + &generic_extra_costs, > + &generic_addrcost_table, > + &generic_regmove_cost, > + &generic_vector_cost, > + &generic_branch_cost, > + &generic_approx_modes, > + 4, /* memmov_cost */ > + 4, /* issue_rate */ > + (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD > + | AARCH64_FUSE_MOVK_MOVK), /* fuseable_ops */ > + 16, /* function_align. */ > + 8, /* jump_align. */ > + 16, /* loop_align. */ > + 2, /* int_reassoc_width. */ > + 4, /* fp_reassoc_width. */ > + 1, /* vec_reassoc_width. */ > + 2, /* min_div_recip_mul_sf. */ > + 2, /* min_div_recip_mul_df. */ > + 0, /* max_case_values. */ > + tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ > + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ > + &generic_prefetch_tune > +}; > + > static const struct tune_params thunderx2t99_tunings = > { > &thunderx2t99_extra_costs, > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 71b2445..bc480ad 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -14326,7 +14326,7 @@ Specify the name of the target processor for which GCC should tune the > performance of the code. Permissible values for this option are: > @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, > @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, > -@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, > +@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, @samp{saphira}, > @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, > @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81}, > @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53}, > -- > 2.7.4 >
On 27/10/17 13:43, Siddhesh Poyarekar wrote: > From: Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org> > > This patch adds an mcpu option for the Qualcomm saphira server part. > Tested on aarch64 and did not find any regressions resulting from this > patch. > > Siddhesh > > 2017-10-27 Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org> > Jim Wilson <jim.wilson@linaro.org> > > gcc/ > * config/aarch64/aarch64-cores.def (saphira): New. > * config/aarch64/aarch64-tune.md: Regenerated. > * doc/invoke.texi (AArch64 Options/-mtune): Add "saphira". > * gcc/config/aarch64/aarch64.c (saphira_tunings): New. OK. R. > > Change-Id: I23c4a1ab74e4376c3800cb1481c508bc27418508 > --- > gcc/config/aarch64/aarch64-cores.def | 5 +++++ > gcc/config/aarch64/aarch64-tune.md | 2 +- > gcc/config/aarch64/aarch64.c | 28 ++++++++++++++++++++++++++++ > gcc/doc/invoke.texi | 2 +- > 4 files changed, 35 insertions(+), 2 deletions(-) > > diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def > index 16e4485..cdf047c 100644 > --- a/gcc/config/aarch64/aarch64-cores.def > +++ b/gcc/config/aarch64/aarch64-cores.def > @@ -86,6 +86,11 @@ AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR > AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1) > AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1) > > +/* ARMv8.3-A Architecture Processors. */ > + > +/* Qualcomm ('Q') cores. */ > +AARCH64_CORE("saphira", saphira, falkor, 8_3A, AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira, 0x51, 0xC01, -1) > + > /* ARMv8-A big.LITTLE implementations. */ > > AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1) > diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md > index 7fcd6cb..7b3a746 100644 > --- a/gcc/config/aarch64/aarch64-tune.md > +++ b/gcc/config/aarch64/aarch64-tune.md > @@ -1,5 +1,5 @@ > ;; -*- buffer-read-only: t -*- > ;; Generated automatically by gentune.sh from aarch64-cores.def > (define_attr "tune" > - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" > + "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" > (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > index d1aaf19..f554ffb 100644 > --- a/gcc/config/aarch64/aarch64.c > +++ b/gcc/config/aarch64/aarch64.c > @@ -822,6 +822,34 @@ static const struct tune_params qdf24xx_tunings = > &qdf24xx_prefetch_tune > }; > > +/* Tuning structure for the Qualcomm Saphira core. Default to falkor values > + for now. */ > +static const struct tune_params saphira_tunings = > +{ > + &generic_extra_costs, > + &generic_addrcost_table, > + &generic_regmove_cost, > + &generic_vector_cost, > + &generic_branch_cost, > + &generic_approx_modes, > + 4, /* memmov_cost */ > + 4, /* issue_rate */ > + (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD > + | AARCH64_FUSE_MOVK_MOVK), /* fuseable_ops */ > + 16, /* function_align. */ > + 8, /* jump_align. */ > + 16, /* loop_align. */ > + 2, /* int_reassoc_width. */ > + 4, /* fp_reassoc_width. */ > + 1, /* vec_reassoc_width. */ > + 2, /* min_div_recip_mul_sf. */ > + 2, /* min_div_recip_mul_df. */ > + 0, /* max_case_values. */ > + tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ > + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ > + &generic_prefetch_tune > +}; > + > static const struct tune_params thunderx2t99_tunings = > { > &thunderx2t99_extra_costs, > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 71b2445..bc480ad 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -14326,7 +14326,7 @@ Specify the name of the target processor for which GCC should tune the > performance of the code. Permissible values for this option are: > @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, > @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, > -@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, > +@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, @samp{saphira}, > @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, > @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81}, > @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53}, >
On 3 November 2017 at 15:50, Richard Earnshaw <Richard.Earnshaw@foss.arm.com> wrote: >> 2017-10-27 Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org> >> Jim Wilson <jim.wilson@linaro.org> >> >> gcc/ >> * config/aarch64/aarch64-cores.def (saphira): New. >> * config/aarch64/aarch64-tune.md: Regenerated. >> * doc/invoke.texi (AArch64 Options/-mtune): Add "saphira". >> * gcc/config/aarch64/aarch64.c (saphira_tunings): New. > > OK. Thanks, I don't have commit access, can you please push for me? Alternatively, may I request commit access? Siddhesh
On 03/11/17 12:45, Siddhesh Poyarekar wrote: > On 3 November 2017 at 15:50, Richard Earnshaw > <Richard.Earnshaw@foss.arm.com> wrote: >>> 2017-10-27 Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org> >>> Jim Wilson <jim.wilson@linaro.org> >>> >>> gcc/ >>> * config/aarch64/aarch64-cores.def (saphira): New. >>> * config/aarch64/aarch64-tune.md: Regenerated. >>> * doc/invoke.texi (AArch64 Options/-mtune): Add "saphira". >>> * gcc/config/aarch64/aarch64.c (saphira_tunings): New. >> >> OK. > > Thanks, I don't have commit access, can you please push for me? > Alternatively, may I request commit access? > > Siddhesh > Committed. R.
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 16e4485..cdf047c 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -86,6 +86,11 @@ AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1) AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1) +/* ARMv8.3-A Architecture Processors. */ + +/* Qualcomm ('Q') cores. */ +AARCH64_CORE("saphira", saphira, falkor, 8_3A, AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira, 0x51, 0xC01, -1) + /* ARMv8-A big.LITTLE implementations. */ AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1) diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index 7fcd6cb..7b3a746 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" + "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d1aaf19..f554ffb 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -822,6 +822,34 @@ static const struct tune_params qdf24xx_tunings = &qdf24xx_prefetch_tune }; +/* Tuning structure for the Qualcomm Saphira core. Default to falkor values + for now. */ +static const struct tune_params saphira_tunings = +{ + &generic_extra_costs, + &generic_addrcost_table, + &generic_regmove_cost, + &generic_vector_cost, + &generic_branch_cost, + &generic_approx_modes, + 4, /* memmov_cost */ + 4, /* issue_rate */ + (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD + | AARCH64_FUSE_MOVK_MOVK), /* fuseable_ops */ + 16, /* function_align. */ + 8, /* jump_align. */ + 16, /* loop_align. */ + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &generic_prefetch_tune +}; + static const struct tune_params thunderx2t99_tunings = { &thunderx2t99_extra_costs, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 71b2445..bc480ad 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14326,7 +14326,7 @@ Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, -@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, +@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, @samp{saphira}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81}, @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53},
From: Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org> This patch adds an mcpu option for the Qualcomm saphira server part. Tested on aarch64 and did not find any regressions resulting from this patch. Siddhesh 2017-10-27 Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org> Jim Wilson <jim.wilson@linaro.org> gcc/ * config/aarch64/aarch64-cores.def (saphira): New. * config/aarch64/aarch64-tune.md: Regenerated. * doc/invoke.texi (AArch64 Options/-mtune): Add "saphira". * gcc/config/aarch64/aarch64.c (saphira_tunings): New. Change-Id: I23c4a1ab74e4376c3800cb1481c508bc27418508 --- gcc/config/aarch64/aarch64-cores.def | 5 +++++ gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/config/aarch64/aarch64.c | 28 ++++++++++++++++++++++++++++ gcc/doc/invoke.texi | 2 +- 4 files changed, 35 insertions(+), 2 deletions(-)