From patchwork Mon Oct 9 20:20:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: will schmidt X-Patchwork-Id: 823495 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-463818-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Y4LdW7Nf"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y9s870jxcz9t2Z for ; Tue, 10 Oct 2017 07:21:10 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:reply-to:to:cc:content-type:date:mime-version :content-transfer-encoding:message-id; q=dns; s=default; b=GMXoQ wlYCMclz7cJ/8msExYEi92xjCz+CUz17M9qpPocIlPBQwr274xf9F/tbHjR9hCC+ ikPdsP76VdQHvRfFTvr428+N38aUL/1sr7GwQsWkT3ZV819+Gq5bbn4Mt5oPnwsw O4FuB+JFs3vs6XhBMqX1TteccRyrymySyGNlrA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:reply-to:to:cc:content-type:date:mime-version :content-transfer-encoding:message-id; s=default; bh=3NXxmDw8eNM mTNgdjbo2iv8I1lo=; b=Y4LdW7NfzWYrLKJrCUFCjLLHG3qRmKEEyG/7IncRSyX DFSVima+tC1wSEXZS9ls4SF7Am6NjjUUAVptaMWJRVs4txlnVFgPon2/qlh5Zlw3 oRB1fMfPlAZ1jJLmoSxEuEiwlxzIA18G9WKG+NtEfCzqgMJlDA0cZZEaOKmHUCL8 = Received: (qmail 44706 invoked by alias); 9 Oct 2017 20:21:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 44365 invoked by uid 89); 9 Oct 2017 20:20:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=H*MI:141 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Oct 2017 20:20:57 +0000 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v99KJZAw020553 for ; Mon, 9 Oct 2017 16:20:52 -0400 Received: from e19.ny.us.ibm.com (e19.ny.us.ibm.com [129.33.205.209]) by mx0b-001b2d01.pphosted.com with ESMTP id 2dgabpjspe-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 09 Oct 2017 16:20:51 -0400 Received: from localhost by e19.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 9 Oct 2017 16:20:48 -0400 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v99KKlUU54460526; Mon, 9 Oct 2017 20:20:47 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9CF03AE03B; Mon, 9 Oct 2017 16:21:25 -0400 (EDT) Received: from [9.10.86.107] (unknown [9.10.86.107]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id 566DBAE034; Mon, 9 Oct 2017 16:21:25 -0400 (EDT) Subject: [PATCH, rs6000] testcase coverage for vec_cmp builtins From: Will Schmidt Reply-To: will_schmidt@vnet.ibm.com To: GCC Patches Cc: Segher Boessenkool , Bill Schmidt , David Edelsohn Date: Mon, 09 Oct 2017 15:20:46 -0500 Mime-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 17100920-0056-0000-0000-000003D714D0 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007869; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000235; SDB=6.00928777; UDB=6.00467444; IPR=6.00709049; BA=6.00005631; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017463; XFM=3.00000015; UTC=2017-10-09 20:20:49 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17100920-0057-0000-0000-0000080E14CE Message-Id: <1507580446.26707.141.camel@brimstone.rchland.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-10-09_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1710090295 X-IsSubscribed: yes Hi, Add testcase coverage for the vec_cmp builtins. Tested on P6 and newer. OK for trunk? Thanks, -Will [testsuite] * gcc.target/powerpc/fold-vec-cmp-char.c: New. * gcc.target/powerpc/fold-vec-cmp-double.c: New. * gcc.target/powerpc/fold-vec-cmp-float.c: New. * gcc.target/powerpc/fold-vec-cmp-int.c: New. * gcc.target/powerpc/fold-vec-cmp-longlong.c: New. * gcc.target/powerpc/fold-vec-cmp-short.c: New. diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.c new file mode 100644 index 0000000..3a1aa60 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.c @@ -0,0 +1,86 @@ +/* Verify that overloaded built-ins for vec_cmp{eq,ge,gt,le,lt,ne} with + char inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include + +vector bool char +test3_eq (vector signed char x, vector signed char y) +{ + return vec_cmpeq (x, y); +} + +vector bool char +test6_eq (vector unsigned char x, vector unsigned char y) +{ + return vec_cmpeq (x, y); +} + +vector bool char +test3_ge (vector signed char x, vector signed char y) +{ + return vec_cmpge (x, y); +} + +vector bool char +test6_ge (vector unsigned char x, vector unsigned char y) +{ + return vec_cmpge (x, y); +} + +vector bool char +test3_gt (vector signed char x, vector signed char y) +{ + return vec_cmpgt (x, y); +} + +vector bool char +test6_gt (vector unsigned char x, vector unsigned char y) +{ + return vec_cmpgt (x, y); +} + +vector bool char +test3_le (vector signed char x, vector signed char y) +{ + return vec_cmple (x, y); +} + +vector bool char +test6_le (vector unsigned char x, vector unsigned char y) +{ + return vec_cmple (x, y); +} + +vector bool char +test3_lt (vector signed char x, vector signed char y) +{ + return vec_cmplt (x, y); +} + +vector bool char +test6_lt (vector unsigned char x, vector unsigned char y) +{ + return vec_cmplt (x, y); +} + +vector bool char +test3_ne (vector signed char x, vector signed char y) +{ + return vec_cmpne (x, y); +} + +vector bool char +test6_ne (vector unsigned char x, vector unsigned char y) +{ + return vec_cmpne (x, y); +} + +/* { dg-final { scan-assembler-times "vcmpequb" 4 } } */ +/* { dg-final { scan-assembler-times "vcmpgtsb" 4 } } */ +/* { dg-final { scan-assembler-times "vcmpgtub" 4 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 6 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-double.c new file mode 100644 index 0000000..9d56862 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-double.c @@ -0,0 +1,51 @@ +/* Verify that overloaded built-ins for vec_cmp with + double inputs for VSX produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include + +vector bool long long +test2_eq (vector double x, vector double y) +{ + return vec_cmpeq (x, y); +} + +vector bool long long +test2_ge (vector double x, vector double y) +{ + return vec_cmpge (x, y); +} + +vector bool long long +test2_gt (vector double x, vector double y) +{ + return vec_cmpgt (x, y); +} + +vector bool long long +test2_le (vector double x, vector double y) +{ + return vec_cmple (x, y); +} + +vector bool long long +test2_lt (vector double x, vector double y) +{ + return vec_cmplt (x, y); +} + + vector bool long long +test2_ne (vector double x, vector double y) +{ + return vec_cmpne (x, y); +} + +/* { dg-final { scan-assembler-times "xvcmpeqdp" 2 } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 2 } } */ +/* { dg-final { scan-assembler-times "xvcmpnedp" 0 } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 2 } } */ +/* { dg-final { scan-assembler-times "fcmpu" 0 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-float.c new file mode 100644 index 0000000..b75250a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-float.c @@ -0,0 +1,51 @@ +/* Verify that overloaded built-ins for vec_cmp with float + inputs for VSX produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include + +vector bool int +test1_eq (vector float x, vector float y) +{ + return vec_cmpeq (x, y); +} + +vector bool int +test1_ge (vector float x, vector float y) +{ + return vec_cmpge (x, y); +} + +vector bool int +test1_gt (vector float x, vector float y) +{ + return vec_cmpgt (x, y); +} + +vector bool int +test1_le (vector float x, vector float y) +{ + return vec_cmple (x, y); +} + +vector bool int +test1_lt (vector float x, vector float y) +{ + return vec_cmplt (x, y); +} + +vector bool int +test1_ne (vector float x, vector float y) +{ + return vec_cmpne (x, y); +} + +/* { dg-final { scan-assembler-times "xvcmpeqsp" 2 } } */ +/* { dg-final { scan-assembler-times "xvcmpgtsp" 2 } } */ +/* { dg-final { scan-assembler-times "xvcmpnesp" 0 } } */ +/* { dg-final { scan-assembler-times "xvcmpgesp" 2 } } */ +/* { dg-final { scan-assembler-times "fcmpu" 0 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.c new file mode 100644 index 0000000..d53994d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.c @@ -0,0 +1,86 @@ +/* Verify that overloaded built-ins for vec_cmp with int + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include + +vector bool int +test3_eq (vector signed int x, vector signed int y) +{ + return vec_cmpeq (x, y); +} + +vector bool int +test6_eq (vector unsigned int x, vector unsigned int y) +{ + return vec_cmpeq (x, y); +} + +vector bool int +test3_ge (vector signed int x, vector signed int y) +{ + return vec_cmpge (x, y); +} + +vector bool int +test6_ge (vector unsigned int x, vector unsigned int y) +{ + return vec_cmpge (x, y); +} + +vector bool int +test3_gt (vector signed int x, vector signed int y) +{ + return vec_cmpgt (x, y); +} + +vector bool int +test6_gt (vector unsigned int x, vector unsigned int y) +{ + return vec_cmpgt (x, y); +} + +vector bool int +test3_le (vector signed int x, vector signed int y) +{ + return vec_cmple (x, y); +} + +vector bool int +test6_le (vector unsigned int x, vector unsigned int y) +{ + return vec_cmple (x, y); +} + +vector bool int +test3_lt (vector signed int x, vector signed int y) +{ + return vec_cmplt (x, y); +} + +vector bool int +test6_lt (vector unsigned int x, vector unsigned int y) +{ + return vec_cmplt (x, y); +} + +vector bool int +test3_ne (vector signed int x, vector signed int y) +{ + return vec_cmpne (x, y); +} + +vector bool int +test6_ne (vector unsigned int x, vector unsigned int y) +{ + return vec_cmpne (x, y); +} + +/* { dg-final { scan-assembler-times "vcmpequw" 4 } } */ +/* { dg-final { scan-assembler-times "vcmpgtsw" 4 } } */ +/* { dg-final { scan-assembler-times "vcmpgtuw" 4 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 6 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c new file mode 100644 index 0000000..536ee75 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c @@ -0,0 +1,86 @@ +/* Verify that overloaded built-ins for vec_cmp with long long + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include + +vector bool long long +test3_eq (vector signed long long x, vector signed long long y) +{ + return vec_cmpeq (x, y); +} + +vector bool long long +test6_eq (vector unsigned long long x, vector unsigned long long y) +{ + return vec_cmpeq (x, y); +} + +vector bool long long +test3_ge (vector signed long long x, vector signed long long y) +{ + return vec_cmpge (x, y); +} + +vector bool long long +test6_ge (vector unsigned long long x, vector unsigned long long y) +{ + return vec_cmpge (x, y); +} + +vector bool long long +test3_gt (vector signed long long x, vector signed long long y) +{ + return vec_cmpgt (x, y); +} + +vector bool long long +test6_gt (vector unsigned long long x, vector unsigned long long y) +{ + return vec_cmpgt (x, y); +} + +vector bool long long +test3_le (vector signed long long x, vector signed long long y) +{ + return vec_cmple (x, y); +} + +vector bool long long +test6_le (vector unsigned long long x, vector unsigned long long y) +{ + return vec_cmple (x, y); +} + +vector bool long long +test3_lt (vector signed long long x, vector signed long long y) +{ + return vec_cmplt (x, y); +} + +vector bool long long +test6_lt (vector unsigned long long x, vector unsigned long long y) +{ + return vec_cmplt (x, y); +} + +vector bool long long +test3_ne (vector signed long long x, vector signed long long y) +{ + return vec_cmpne (x, y); +} + +vector bool long long +test6_ne (vector unsigned long long x, vector unsigned long long y) +{ + return vec_cmpne (x, y); +} + +/* { dg-final { scan-assembler-times "vcmpequd" 4 } } */ +/* { dg-final { scan-assembler-times "vcmpgtsd" 4 } } */ +/* { dg-final { scan-assembler-times "vcmpgtud" 4 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 6 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.c new file mode 100644 index 0000000..6067669 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.c @@ -0,0 +1,87 @@ +/* Verify that overloaded built-ins for vec_cmp with short + inputs produce the right code. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include + +vector bool short +test3_eq (vector signed short x, vector signed short y) +{ + return vec_cmpeq (x, y); +} + +vector bool short +test6_eq (vector unsigned short x, vector unsigned short y) +{ + return vec_cmpeq (x, y); +} + +vector bool short +test3_ge (vector signed short x, vector signed short y) +{ + return vec_cmpge (x, y); +} + +vector bool short +test6_ge (vector unsigned short x, vector unsigned short y) +{ + return vec_cmpge (x, y); +} + +vector bool short +test3_gt (vector signed short x, vector signed short y) +{ + return vec_cmpgt (x, y); +} + +vector bool short +test6_gt (vector unsigned short x, vector unsigned short y) +{ + return vec_cmpgt (x, y); +} + + +vector bool short +test3_le (vector signed short x, vector signed short y) +{ + return vec_cmple (x, y); +} + +vector bool short +test6_le (vector unsigned short x, vector unsigned short y) +{ + return vec_cmple (x, y); +} + +vector bool short +test3_lt (vector signed short x, vector signed short y) +{ + return vec_cmplt (x, y); +} + +vector bool short +test6_lt (vector unsigned short x, vector unsigned short y) +{ + return vec_cmplt (x, y); +} + +vector bool short +test3_ne (vector signed short x, vector signed short y) +{ + return vec_cmpne (x, y); +} + +vector bool short +test6_ne (vector unsigned short x, vector unsigned short y) +{ + return vec_cmpne (x, y); +} + +/* { dg-final { scan-assembler-times "vcmpequh" 4 } } */ +/* { dg-final { scan-assembler-times "vcmpgtsh" 4 } } */ +/* { dg-final { scan-assembler-times "vcmpgtuh" 4 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 6 } } */ +