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Violators will be prosecuted; Wed, 31 May 2017 15:38:17 -0400 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v4VJcI8Z46137526; Wed, 31 May 2017 19:38:18 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2ADD2AE043; Wed, 31 May 2017 15:38:15 -0400 (EDT) Received: from [9.10.86.107] (unknown [9.10.86.107]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id C6F1CAE03B; Wed, 31 May 2017 15:38:14 -0400 (EDT) Subject: [PATCH v2, rs6000] Fold vector absolutes in GIMPLE From: Will Schmidt Reply-To: will_schmidt@vnet.ibm.com To: GCC Patches Cc: Richard Biener , Segher Boessenkool , David Edelsohn , Bill Schmidt Date: Wed, 31 May 2017 14:38:15 -0500 Mime-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 17053119-0052-0000-0000-00000210E583 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007150; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000212; SDB=6.00868333; UDB=6.00431518; IPR=6.00648212; BA=6.00005388; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00015660; XFM=3.00000015; UTC=2017-05-31 19:38:18 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17053119-0053-0000-0000-000050C7EA55 Message-Id: <1496259495.15163.199.camel@brimstone.rchland.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-31_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1705310353 X-IsSubscribed: yes Hi, Add support for early expansion of vector absolute built-ins. [V2] Per reviews and feedback, skip the early folding for integral types based on a check against TYPE_OVERFLOW_WRAPS(arg0). Added test variants to exercise the -fwrapv option during this folding. OK for trunk? (bootstraps running, pending review). [gcc] 2017-05-31 Will Schmidt * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of vector absolute builtins. [gcc/testsuite] 2017-05-31 Will Schmidt * gcc.target/powerpc/fold-vec-abs-char.c: New. * gcc.target/powerpc/fold-vec-abs-floatdouble.c: New. * gcc.target/powerpc/fold-vec-abs-int.c: New. * gcc.target/powerpc/fold-vec-abs-longlong.c: New. * gcc.target/powerpc/fold-vec-abs-short.c: New. * gcc.target/powerpc/fold-vec-abs-char-fwrapv.c: New. * gcc.target/powerpc/fold-vec-abs-int-fwrapv.c: New. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c: New. * gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: New. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index dac673c..46d281a 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -17333,6 +17333,24 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) gsi_replace (gsi, g, true); return true; } + /* flavors of vec_abs. */ + case ALTIVEC_BUILTIN_ABS_V16QI: + case ALTIVEC_BUILTIN_ABS_V8HI: + case ALTIVEC_BUILTIN_ABS_V4SI: + case ALTIVEC_BUILTIN_ABS_V4SF: + case P8V_BUILTIN_ABS_V2DI: + case VSX_BUILTIN_XVABSDP: + { + arg0 = gimple_call_arg (stmt, 0); + if ( INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE(arg0))) + && ! TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE(arg0)))) + return false; + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, ABS_EXPR, arg0); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } default: break; } diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char-fwrapv.c new file mode 100644 index 0000000..739f06e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char-fwrapv.c @@ -0,0 +1,18 @@ +/* Verify that overloaded built-ins for vec_abs with char + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -fwrapv" } */ + +#include + +vector signed char +test2 (vector signed char x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsububm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsb" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char.c new file mode 100644 index 0000000..239c919 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-char.c @@ -0,0 +1,18 @@ +/* Verify that overloaded built-ins for vec_abs with char + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector signed char +test2 (vector signed char x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsububm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsb" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-floatdouble.c new file mode 100644 index 0000000..1a08618 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-floatdouble.c @@ -0,0 +1,23 @@ +/* Verify that overloaded built-ins for vec_abs with float and + double inputs for VSX produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include + +vector float +test1 (vector float x) +{ + return vec_abs (x); +} + +vector double +test2 (vector double x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "xvabssp" 1 } } */ +/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c new file mode 100644 index 0000000..34dead4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.c @@ -0,0 +1,18 @@ +/* Verify that overloaded built-ins for vec_abs with int + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -fwrapv" } */ + +#include + +vector signed int +test1 (vector signed int x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c new file mode 100644 index 0000000..77d9ca5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.c @@ -0,0 +1,18 @@ +/* Verify that overloaded built-ins for vec_abs with int + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector signed int +test1 (vector signed int x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsubuwm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c new file mode 100644 index 0000000..934618b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c @@ -0,0 +1,18 @@ +/* Verify that overloaded built-ins for vec_abs with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2 -fwrapv" } */ + +#include + +vector signed long long +test3 (vector signed long long x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsubudm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c new file mode 100644 index 0000000..5b59d19 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c @@ -0,0 +1,18 @@ +/* Verify that overloaded built-ins for vec_abs with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include + +vector signed long long +test3 (vector signed long long x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsubudm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c new file mode 100644 index 0000000..2562179 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short-fwrapv.c @@ -0,0 +1,18 @@ +/* Verify that overloaded built-ins for vec_abs with short + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -fwrapv" } */ + +#include + +vector signed short +test3 (vector signed short x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsubuhm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsh" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c new file mode 100644 index 0000000..d312000 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-short.c @@ -0,0 +1,18 @@ +/* Verify that overloaded built-ins for vec_abs with short + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector signed short +test3 (vector signed short x) +{ + return vec_abs (x); +} + +/* { dg-final { scan-assembler-times "vspltisw|vxor" 1 } } */ +/* { dg-final { scan-assembler-times "vsubuhm" 1 } } */ +/* { dg-final { scan-assembler-times "vmaxsh" 1 } } */