@@ -17408,6 +17408,76 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
gsi_replace (gsi, g, true);
return true;
}
+ /* Flavors of vec_rotate_left . */
+ case ALTIVEC_BUILTIN_VRLB:
+ case ALTIVEC_BUILTIN_VRLH:
+ case ALTIVEC_BUILTIN_VRLW:
+ case P8V_BUILTIN_VRLD:
+ {
+ arg0 = gimple_call_arg (stmt, 0);
+ arg1 = gimple_call_arg (stmt, 1);
+ lhs = gimple_call_lhs (stmt);
+ gimple *g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_replace (gsi, g, true);
+ return true;
+ }
+ /* Flavors of vector shift right algebraic. vec_sra{b,h,w} -> vsra{b,h,w}. */
+ case ALTIVEC_BUILTIN_VSRAB:
+ case ALTIVEC_BUILTIN_VSRAH:
+ case ALTIVEC_BUILTIN_VSRAW:
+ case P8V_BUILTIN_VSRAD:
+ {
+ arg0 = gimple_call_arg (stmt, 0);
+ arg1 = gimple_call_arg (stmt, 1);
+ lhs = gimple_call_lhs (stmt);
+ gimple *g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_replace (gsi, g, true);
+ return true;
+ }
+ /* Flavors of vector shift left. builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
+ case ALTIVEC_BUILTIN_VSLB:
+ case ALTIVEC_BUILTIN_VSLH:
+ case ALTIVEC_BUILTIN_VSLW:
+ case P8V_BUILTIN_VSLD:
+ {
+ arg0 = gimple_call_arg (stmt, 0);
+ arg1 = gimple_call_arg (stmt, 1);
+ lhs = gimple_call_lhs (stmt);
+ gimple *g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_replace (gsi, g, true);
+ return true;
+ }
+ /* Flavors of vector shift right. */
+ case ALTIVEC_BUILTIN_VSRB:
+ case ALTIVEC_BUILTIN_VSRH:
+ case ALTIVEC_BUILTIN_VSRW:
+ case P8V_BUILTIN_VSRD:
+ {
+ arg0 = gimple_call_arg (stmt, 0);
+ arg1 = gimple_call_arg (stmt, 1);
+ lhs = gimple_call_lhs (stmt);
+ gimple *g;
+ /* convert arg0 to unsigned */
+ arg0 = convert(unsigned_type_for(TREE_TYPE(arg0)),arg0);
+ tree arg0_uns = create_tmp_reg_or_ssa_name(unsigned_type_for(TREE_TYPE(arg0)));
+ g = gimple_build_assign(arg0_uns,arg0);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_insert_before (gsi, g, GSI_SAME_STMT);
+ /* convert lhs to unsigned and do the shift. */
+ tree lhs_uns = create_tmp_reg_or_ssa_name(unsigned_type_for(TREE_TYPE(lhs)));
+ g = gimple_build_assign (lhs_uns, RSHIFT_EXPR, arg0_uns, arg1);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_insert_before (gsi, g, GSI_SAME_STMT);
+ /* convert lhs back to a signed type for the return. */
+ lhs_uns = convert(signed_type_for(TREE_TYPE(lhs)),lhs_uns);
+ g = gimple_build_assign(lhs,lhs_uns);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_replace (gsi, g, true);
+ return true;
+ }
default:
break;
}
@@ -19128,6 +19198,14 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
h.uns_p[2] = 1;
break;
+ /* unsigned second arguments (vector shift right). */
+ case ALTIVEC_BUILTIN_VSRB:
+ case ALTIVEC_BUILTIN_VSRH:
+ case ALTIVEC_BUILTIN_VSRW:
+ case P8V_BUILTIN_VSRD:
+ h.uns_p[2] = 1;
+ break;
+
default:
break;
}
new file mode 100644
@@ -0,0 +1,66 @@
+/* Verify that overloaded built-ins for vec_sl with char
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+//# vec_sl - shift left
+//# vec_sr - shift right
+//# vec_sra - shift right algebraic
+//# vec_rl - rotate left
+
+vector signed char
+testsl_signed (vector signed char x, vector unsigned char y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned char
+testsl_unsigned (vector unsigned char x, vector unsigned char y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed char
+testsr_signed (vector signed char x, vector unsigned char y)
+{
+ return vec_sr (x, y);
+}
+
+vector unsigned char
+testsr_unsigned (vector unsigned char x, vector unsigned char y)
+{
+ return vec_sr (x, y);
+}
+
+vector signed char
+testsra_signed (vector signed char x, vector unsigned char y)
+{
+ return vec_sra (x, y);
+}
+
+vector unsigned char
+testsra_unsigned (vector unsigned char x, vector unsigned char y)
+{
+ return vec_sra (x, y);
+}
+
+vector signed char
+testrl_signed (vector signed char x, vector unsigned char y)
+{
+ return vec_rl (x, y);
+}
+
+vector unsigned char
+testrl_unsigned (vector unsigned char x, vector unsigned char y)
+{
+ return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslb" 2 } } */
+/* { dg-final { scan-assembler-times "vsrb" 2 } } */
+/* { dg-final { scan-assembler-times "vsrab" 2 } } */
+/* { dg-final { scan-assembler-times "vrlb" 2 } } */
new file mode 100644
@@ -0,0 +1,61 @@
+/* Verify that overloaded built-ins for vec_sl with int
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed int
+testsl_signed (vector signed int x, vector unsigned int y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned int
+testsl_unsigned (vector unsigned int x, vector unsigned int y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed int
+testsr_signed (vector signed int x, vector unsigned int y)
+{
+ return vec_sr (x, y);
+}
+
+vector unsigned int
+testsr_unsigned (vector unsigned int x, vector unsigned int y)
+{
+ return vec_sr (x, y);
+}
+
+vector signed int
+testsra_signed (vector signed int x, vector unsigned int y)
+{
+ return vec_sra (x, y);
+}
+
+vector unsigned int
+testsra_unsigned (vector unsigned int x, vector unsigned int y)
+{
+ return vec_sra (x, y);
+}
+
+vector signed int
+testrl_signed (vector signed int x, vector unsigned int y)
+{
+ return vec_rl (x, y);
+}
+
+vector unsigned int
+testrl_unsigned (vector unsigned int x, vector unsigned int y)
+{
+ return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslw" 2 } } */
+/* { dg-final { scan-assembler-times "vsrw" 2 } } */
+/* { dg-final { scan-assembler-times "vsraw" 2 } } */
+/* { dg-final { scan-assembler-times "vrlw" 2 } } */
new file mode 100644
@@ -0,0 +1,63 @@
+/* Verify that overloaded built-ins for vec_sl with long long
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed long long
+testsl_signed (vector signed long long x, vector unsigned long long y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned long long
+testsl_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed long long
+testsr_signed (vector signed long long x, vector unsigned long long y)
+{
+ return vec_sr (x, y);
+}
+
+vector unsigned long long
+testsr_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_sr (x, y);
+}
+
+vector signed long long
+testsra_signed (vector signed long long x, vector unsigned long long y)
+{
+ return vec_sra (x, y);
+}
+
+/* watch for PR 79544 here (vsrd / vsrad issue) */
+vector unsigned long long
+testsra_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_sra (x, y);
+}
+
+vector signed long long
+testrl_signed (vector signed long long x, vector unsigned long long y)
+{
+ return vec_rl (x, y);
+}
+
+vector unsigned long long
+testrl_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsld" 2 } } */
+/* { dg-final { scan-assembler-times "vsrd" 2 } } */
+/* { dg-final { scan-assembler-times "vsrad" 2 } } */
+/* { dg-final { scan-assembler-times "vrld" 2 } } */
+
new file mode 100644
@@ -0,0 +1,61 @@
+/* Verify that overloaded built-ins for vec_sl with short
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed short
+testsl_signed (vector signed short x, vector unsigned short y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned short
+testsl_unsigned (vector unsigned short x, vector unsigned short y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed short
+testsr_signed (vector signed short x, vector unsigned short y)
+{
+ return vec_sr (x, y);
+}
+
+vector unsigned short
+testsr_unsigned (vector unsigned short x, vector unsigned short y)
+{
+ return vec_sr (x, y);
+}
+
+vector signed short
+testsra_signed (vector signed short x, vector unsigned short y)
+{
+ return vec_sra (x, y);
+}
+
+vector unsigned short
+testsra_unsigned (vector unsigned short x, vector unsigned short y)
+{
+ return vec_sra (x, y);
+}
+
+vector signed short
+testrl_signed (vector signed short x, vector unsigned short y)
+{
+ return vec_rl (x, y);
+}
+
+vector unsigned short
+testrl_unsigned (vector unsigned short x, vector unsigned short y)
+{
+ return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslh" 2 } } */
+/* { dg-final { scan-assembler-times "vsrh" 2 } } */
+/* { dg-final { scan-assembler-times "vsrah" 2 } } */
+/* { dg-final { scan-assembler-times "vrlh" 2 } } */