From patchwork Mon Dec 19 17:01:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: will schmidt X-Patchwork-Id: 707163 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tj6dq41nRz9syB for ; Tue, 20 Dec 2016 04:01:51 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="wsRdCuNa"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:reply-to:to:cc:content-type:date:mime-version :content-transfer-encoding:message-id; q=dns; s=default; b=GH1m7 VQHGdEbpwjQRsgaH0W34EfGITLPunRRaThrZ9fvuuAige2DGd4XFvnRHmWiIlBq8 JGSbSrR0KG/fb2OCbNsG8j25k6RpRvHtUV/QVoPEm2tgJp7D73pJ5A73Wdewf05u W5D1QWJiE/Ww5jlmRGBFaYs8USoeb/DJoBWMMA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:reply-to:to:cc:content-type:date:mime-version :content-transfer-encoding:message-id; s=default; bh=9VzlB0oojXJ 6H+bVjtChjoQvDRA=; b=wsRdCuNahuB0rNgYQuDjWr8y1GIonRzgD/J0CEOVWzh r27uI4EiVxlNy+HmRSUAZs31wAfoJFx7X2WR8EgBky/NQNO8UMI6Nem0HWEUifQg pJ/WjD4IJRNAQ64NvsgCyryZxOQtx6q+0lhwAjI/PTvXgkrKom0fTPFaAD9GSNVo = Received: (qmail 76213 invoked by alias); 19 Dec 2016 17:01:32 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 76134 invoked by uid 89); 19 Dec 2016 17:01:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=Multiply, multiply, dgskipif, dg-skip-if X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 19 Dec 2016 17:01:28 +0000 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uBJGww3u138272 for ; Mon, 19 Dec 2016 12:01:26 -0500 Received: from e37.co.us.ibm.com (e37.co.us.ibm.com [32.97.110.158]) by mx0a-001b2d01.pphosted.com with ESMTP id 27ecg39bdx-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 19 Dec 2016 12:01:26 -0500 Received: from localhost by e37.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 19 Dec 2016 10:01:21 -0700 Received: from b03cxnp08025.gho.boulder.ibm.com (b03cxnp08025.gho.boulder.ibm.com [9.17.130.17]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id DAA0619D8059; Mon, 19 Dec 2016 10:00:39 -0700 (MST) Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id uBJH1LJk11010326; Mon, 19 Dec 2016 10:01:21 -0700 Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 32B4ABE04A; Mon, 19 Dec 2016 10:01:21 -0700 (MST) Received: from [9.10.86.107] (unknown [9.10.86.107]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP id C7AACBE039; Mon, 19 Dec 2016 10:01:20 -0700 (MST) Subject: [PATCH, rs6000] Fold vector multiply built-ins in GIMPLE From: Will Schmidt Reply-To: will_schmidt@vnet.ibm.com To: GCC Patches Cc: Segher Boessenkool , David Edelsohn , Bill Schmidt Date: Mon, 19 Dec 2016 11:01:19 -0600 Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16121917-0024-0000-0000-0000154EFC18 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006278; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000198; SDB=6.00796077; UDB=6.00386318; IPR=6.00573891; BA=6.00004986; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00013658; XFM=3.00000011; UTC=2016-12-19 17:01:23 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16121917-0025-0000-0000-00004717CD27 Message-Id: <1482166879.13393.55.camel@brimstone.rchland.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-12-19_14:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1612190209 X-IsSubscribed: yes Hi, This patch implements folding of the vector Multiply built-ins. As part of this patch, I have also marked variables in an existing testcase (mult-even-odd-be-order.c) as volatile, to prevent their being optimized out, which happens once this vector multiply folding was able to occur. Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions. Is this ok for trunk? Thanks, -Will [gcc] 2016-12-19 Will Schmidt * config/rs6000/rs6000.c: Add handling for early expansion of vector multiply builtins. [gcc/testsuite] 2016-12-19 Will Schmidt * testsuite/gcc.dg/vmx/mult-even-odd-be-order.c : Mark variables as volatile. * testsuite/gcc.target/powerpc/fold-vec-mult-char.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-float.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-floatdouble.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-int.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c : New. * testsuite/gcc.target/powerpc/fold-vec-mult-short.c : New. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 0ab8de3..0d777e8 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16509,6 +16509,36 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) gsi_replace (gsi, g, true); return true; } + /* Even element flavors of vec_mul (signed). */ + case ALTIVEC_BUILTIN_VMULESB: + case ALTIVEC_BUILTIN_VMULESH: + /* Even element flavors of vec_mul (unsigned). */ + case ALTIVEC_BUILTIN_VMULEUB: + case ALTIVEC_BUILTIN_VMULEUH: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* Odd element flavors of vec_mul (signed). */ + case ALTIVEC_BUILTIN_VMULOSB: + case ALTIVEC_BUILTIN_VMULOSH: + /* Odd element flavors of vec_mul (unsigned). */ + case ALTIVEC_BUILTIN_VMULOUB: + case ALTIVEC_BUILTIN_VMULOUH: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } default: break; diff --git a/gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c b/gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c index ff30474..6ba12d0 100644 --- a/gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c +++ b/gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c @@ -4,18 +4,18 @@ static void test() { - vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; - vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3}; - vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7}; - vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3}; - vector unsigned short vusa = {0,1,2,3,4,5,6,7}; - vector unsigned short vusb = {2,3,2,3,2,3,2,3}; - vector signed short vssa = {-4,-3,-2,-1,0,1,2,3}; - vector signed short vssb = {2,-3,2,-3,2,-3,2,-3}; - vector unsigned short vuse, vuso; - vector signed short vsse, vsso; - vector unsigned int vuie, vuio; - vector signed int vsie, vsio; + volatile vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + volatile vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3}; + volatile vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7}; + volatile vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3}; + volatile vector unsigned short vusa = {0,1,2,3,4,5,6,7}; + volatile vector unsigned short vusb = {2,3,2,3,2,3,2,3}; + volatile vector signed short vssa = {-4,-3,-2,-1,0,1,2,3}; + volatile vector signed short vssb = {2,-3,2,-3,2,-3,2,-3}; + volatile vector unsigned short vuse, vuso; + volatile vector signed short vsse, vsso; + volatile vector unsigned int vuie, vuio; + volatile vector signed int vsie, vsio; vuse = vec_mule (vuca, vucb); vuso = vec_mulo (vuca, vucb); diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-char.c new file mode 100644 index 0000000..3f946e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-char.c @@ -0,0 +1,23 @@ +/* Verify that overloaded built-ins for vec_mul with char + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include + +vector signed char +test3 (vector signed char x, vector signed char y) +{ + return vec_mul (x, y); +} + +vector unsigned char +test6 (vector unsigned char x, vector unsigned char y) +{ + return vec_mul (x, y); +} + +/* { dg-final { scan-assembler-times "\[ \t\]vmulesb" 2 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]vmulosb" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-float.c new file mode 100644 index 0000000..619cd6e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-float.c @@ -0,0 +1,17 @@ +/* Verify that overloaded built-ins for vec_mul with float + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mvsx" } */ + +#include + +vector float +test1 (vector float x, vector float y) +{ + return vec_mul (x, y); +} + +/* { dg-final { scan-assembler-times "\[ \t\]xvmulsp" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-floatdouble.c new file mode 100644 index 0000000..685318a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-floatdouble.c @@ -0,0 +1,23 @@ +/* Verify that overloaded built-ins for vec_mul with float and + double inputs for VSX produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -mvsx" } */ + +#include + +vector float +test1 (vector float x, vector float y) +{ + return vec_mul (x, y); +} + +vector double +test2 (vector double x, vector double y) +{ + return vec_mul (x, y); +} + +/* { dg-final { scan-assembler-times "\[ \t\]xvmulsp" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]xvmuldp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c new file mode 100644 index 0000000..d581921 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c @@ -0,0 +1,23 @@ +/* Verify that overloaded built-ins for vec_mul with int + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include + +vector signed int +test3 (vector signed int x, vector signed int y) +{ + return vec_mul (x, y); +} + +vector unsigned int +test6 (vector unsigned int x, vector unsigned int y) +{ + return vec_mul (x, y); +} + +/* { dg-final { scan-assembler-times "\[ \t\]vmuluwm" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c new file mode 100644 index 0000000..a133c5d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c @@ -0,0 +1,25 @@ +/* Verify that overloaded built-ins for vec_mul with __int128 + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target int128 } */ +/* { dg-options "-maltivec -mvsx -mpower8-vector" } */ +/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */ + +#include "altivec.h" + +vector signed __int128 +test1 (vector signed __int128 x, vector signed __int128 y) +{ + return vec_mul (x, y); +} + +vector unsigned __int128 +test2 (vector unsigned __int128 x, vector unsigned __int128 y) +{ + return vec_mul (x, y); +} + +/* { dg-final { scan-assembler-times "\[ \t\]mulld " 6 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]mulhdu" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c new file mode 100644 index 0000000..96c9d01 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c @@ -0,0 +1,25 @@ +/* Verify that overloaded built-ins for vec_mul with __int128 + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_float128_hw_ok } */ +/* { dg-require-effective-target int128 } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-maltivec -mvsx -mcpu=power9 -O2" } */ +/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */ + +#include "altivec.h" + +vector signed __int128 +test1 (vector signed __int128 x, vector signed __int128 y) +{ + return vec_mul (x, y); +} + +vector unsigned __int128 +test2 (vector unsigned __int128 x, vector unsigned __int128 y) +{ + return vec_mul (x, y); +} + +/* { dg-final { scan-assembler-times "\[ \t\]xsmulqp" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c new file mode 100644 index 0000000..cc3d1e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c @@ -0,0 +1,23 @@ +/* Verify that overloaded built-ins for vec_mul with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-maltivec -mvsx -mpower8-vector" } */ + +#include + +vector signed long long +test3 (vector signed long long x, vector signed long long y) +{ + return vec_mul (x, y); +} + +vector unsigned long long +test6 (vector unsigned long long x, vector unsigned long long y) +{ + return vec_mul (x, y); +} + +/* { dg-final { scan-assembler-times "\[ \t\]mulld " 4 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-short.c new file mode 100644 index 0000000..e7504db --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-short.c @@ -0,0 +1,23 @@ +/* Verify that overloaded built-ins for vec_mul with short + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include + +vector signed short +test3 (vector signed short x, vector signed short y) +{ + return vec_mul (x, y); +} + +vector unsigned short +test6 (vector unsigned short x, vector unsigned short y) +{ + return vec_mul (x, y); +} + +/* { dg-final { scan-assembler-times "\[ \t\]vmladduhm" 2 } } */ +