From patchwork Fri Jun 17 17:21:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 637233 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rWRrf22WXz9t0d for ; Sat, 18 Jun 2016 03:22:09 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=GYgyYN45; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; q=dns; s= default; b=BDL0Ijsfyc6ewqA7d1olaubfAgPLoiFybs8/FQDf41w5dRscWoF8Z yAWbgAX4jFeSj35N7uXQZ81p0I6GVRzLzIOiymywvrcFwMl3DIPaRb/wCEckvjas OGDe1prq+eEZpBbHsyTeRx98R8cbfT/TQHXPCwjMKM8c4JVM4ldrjU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=default; bh=8ouBXmoGor0IZIaOIPIAPBdLVME=; b=GYgyYN45Okgele8cxmwRSrJFM1tR kBJOWkaAy2UArP5+8xngqWAegn0ppwC1E/hS4I2DlRFwQDlfI2NDHBAjo2imMxDi ra64r/9tnZwvbrghW6bGBwoqYON/XUiwAsZKZOS25eMCaDNfL6HbgwVwsW1yKhoM TTgIMglABjVW+5c= Received: (qmail 124061 invoked by alias); 17 Jun 2016 17:22:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 124050 invoked by uid 89); 17 Jun 2016 17:22:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.3 required=5.0 tests=BAYES_00, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=isas, neg, UD:elf.h, HContent-Transfer-Encoding:7Bit X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 17 Jun 2016 17:21:51 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 07305F; Fri, 17 Jun 2016 10:22:32 -0700 (PDT) Received: from e108577-lin.localnet (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E99D83F246; Fri, 17 Jun 2016 10:21:48 -0700 (PDT) From: Thomas Preudhomme To: Ramana Radhakrishnan Cc: gcc-patches Subject: Re: [PATCH, libgcc/ARM 1a/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions Date: Fri, 17 Jun 2016 18:21:44 +0100 Message-ID: <14815833.P6VixTcpEo@e108577-lin> User-Agent: KMail/4.13.3 (Linux/3.13.0-85-generic; KDE/4.13.3; x86_64; ; ) In-Reply-To: References: <001301d14d1b$27cc4810$7764d830$@foss.arm.com> MIME-Version: 1.0 X-IsSubscribed: yes On Wednesday 01 June 2016 10:00:52 Ramana Radhakrishnan wrote: > Please fix up the macros, post back and redo the test. Otherwise this > is ok from a quick read. What about the updated patch in attachment? As for the original patch, I've checked that code generation does not change for a number of combinations of ISAs (ARM/Thumb), optimization levels (Os/O2), and architectures (armv4, armv4t, armv5, armv5t, armv5te, armv6, armv6j, armv6k, armv6s-m, armv6kz, armv6t2, armv6z, armv6zk, armv7, armv7-a, armv7e-m, armv7-m, armv7-r, armv7ve, armv8-a, armv8-a+crc, iwmmxt and iwmmxt2). Note, I renumbered this patch 1a to not make the numbering of other patches look strange. The CLZ part is now in patch 1b/7. ChangeLog entries are now as follow: *** gcc/ChangeLog *** 2016-05-23 Thomas Preud'homme * config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to decide whether to prevent some libgcc routines being included for some multilibs rather than __ARM_ARCH_6M__ and add comment to indicate the link between this condition and the one in libgcc/config/arm/lib1func.S. *** gcc/testsuite/ChangeLog *** 2015-11-10 Thomas Preud'homme * lib/target-supports.exp (check_effective_target_arm_cortex_m): Use __ARM_ARCH_ISA_ARM to test for Cortex-M devices. *** libgcc/ChangeLog *** 2016-06-01 Thomas Preud'homme * config/arm/bpabi-v6m.S: Clarify what architectures is the implementation suitable for. * config/arm/lib1funcs.S (__prefer_thumb__): Define among other cases for all Thumb-1 only targets. (NOT_ISA_TARGET_32BIT): Define for Thumb-1 only targets. (THUMB_LDIV0): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__. (EQUIV): Likewise. (ARM_FUNC_ALIAS): Likewise. (umodsi3): Add check to __ARM_ARCH_ISA_THUMB != 1 to guard the idiv version. (modsi3): Likewise. (clzsi2): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__. (clzdi2): Likewise. (ctzsi2): Likewise. (L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__ in guard for checking whether it is defined. (final includes): Test for NOT_ISA_TARGET_32BIT rather than __ARM_ARCH_6M__ and add comment to indicate the connection between this condition and the one in gcc/config/arm/elf.h. * config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__. * config/arm/t-softfp: Likewise. Best regards, Thomas diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index 77f30554d5286bd83aeab0c8dc308cfd44e732dc..246de5492665ba2a0292736a9c53fbaaef184d72 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -148,8 +148,9 @@ while (0) /* Horrible hack: We want to prevent some libgcc routines being included - for some multilibs. */ -#ifndef __ARM_ARCH_6M__ + for some multilibs. The condition should match the one in + libgcc/config/arm/lib1funcs.S. */ +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 #undef L_fixdfsi #undef L_fixunsdfsi #undef L_truncdfsf2 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 04ca17656f2f26dda710e8a0f9ca77dd963ab39b..38151375c29cd007f1cc34ead3aa495606224061 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3320,10 +3320,8 @@ proc check_effective_target_arm_cortex_m { } { return 0 } return [check_no_compiler_messages arm_cortex_m assembly { - #if !defined(__ARM_ARCH_7M__) \ - && !defined (__ARM_ARCH_7EM__) \ - && !defined (__ARM_ARCH_6M__) - #error !__ARM_ARCH_7M__ && !__ARM_ARCH_7EM__ && !__ARM_ARCH_6M__ + #if defined(__ARM_ARCH_ISA_ARM) + #error __ARM_ARCH_ISA_ARM is defined #endif int i; } "-mthumb"] diff --git a/libgcc/config/arm/bpabi-v6m.S b/libgcc/config/arm/bpabi-v6m.S index 5d35aa6afca224613c94cf923f8a2ee8dac949f2..27f33a4e8ced2cb2da8e38f5d78501954ee7363b 100644 --- a/libgcc/config/arm/bpabi-v6m.S +++ b/libgcc/config/arm/bpabi-v6m.S @@ -1,4 +1,5 @@ -/* Miscellaneous BPABI functions. ARMv6M implementation +/* Miscellaneous BPABI functions. Thumb-1 implementation, suitable for ARMv4T, + ARMv6-M and ARMv8-M Baseline like ISA variants. Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by CodeSourcery. diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 375a5135110895faa44267ebee045fd315515027..951dcda1c3bf7f323423a3e2813bdf0501653016 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -124,10 +124,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see && !defined(__thumb2__) \ && (!defined(__THUMB_INTERWORK__) \ || defined (__OPTIMIZE_SIZE__) \ - || defined(__ARM_ARCH_6M__))) + || !__ARM_ARCH_ISA_ARM)) # define __prefer_thumb__ #endif +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1 +#define NOT_ISA_TARGET_32BIT 1 +#endif + /* How to return from a function call depends on the architecture variant. */ #if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) @@ -305,7 +309,7 @@ LSYM(Lend_fde): #ifdef __ARM_EABI__ .macro THUMB_LDIV0 name signed -#if defined(__ARM_ARCH_6M__) +#ifdef NOT_ISA_TARGET_32BIT .ifc \signed, unsigned cmp r0, #0 beq 1f @@ -478,7 +482,7 @@ _L__\name: #else /* !(__INTERWORKING_STUBS__ || __thumb2__) */ -#ifdef __ARM_ARCH_6M__ +#ifdef NOT_ISA_TARGET_32BIT #define EQUIV .thumb_set #else .macro ARM_FUNC_START name sp_section= @@ -510,7 +514,7 @@ SYM (__\name): #endif .endm -#ifndef __ARM_ARCH_6M__ +#ifndef NOT_ISA_TARGET_32BIT .macro ARM_FUNC_ALIAS new old .globl SYM (__\new) EQUIV SYM (__\new), SYM (__\old) @@ -1054,7 +1058,7 @@ ARM_FUNC_START aeabi_uidivmod /* ------------------------------------------------------------------------ */ #ifdef L_umodsi3 -#ifdef __ARM_ARCH_EXT_IDIV__ +#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1 ARM_FUNC_START umodsi3 @@ -1240,7 +1244,7 @@ ARM_FUNC_START aeabi_idivmod /* ------------------------------------------------------------------------ */ #ifdef L_modsi3 -#if defined(__ARM_ARCH_EXT_IDIV__) +#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB != 1 ARM_FUNC_START modsi3 @@ -1515,7 +1519,7 @@ LSYM(Lover12): #endif #ifdef L_clzsi2 -#if defined(__ARM_ARCH_6M__) +#ifdef NOT_ISA_TARGET_32BIT FUNC_START clzsi2 mov r1, #28 mov r3, #1 @@ -1576,7 +1580,7 @@ ARM_FUNC_START clzsi2 #ifdef L_clzdi2 #if !defined(HAVE_ARM_CLZ) -# if defined(__ARM_ARCH_6M__) +# ifdef NOT_ISA_TARGET_32BIT FUNC_START clzdi2 push {r4, lr} # else @@ -1601,7 +1605,7 @@ ARM_FUNC_START clzdi2 bl __clzsi2 # endif 2: -# if defined(__ARM_ARCH_6M__) +# ifdef NOT_ISA_TARGET_32BIT pop {r4, pc} # else RETLDM r4 @@ -1623,7 +1627,7 @@ ARM_FUNC_START clzdi2 #endif /* L_clzdi2 */ #ifdef L_ctzsi2 -#if defined(__ARM_ARCH_6M__) +#ifdef NOT_ISA_TARGET_32BIT FUNC_START ctzsi2 neg r1, r0 and r0, r0, r1 @@ -1738,7 +1742,7 @@ ARM_FUNC_START ctzsi2 /* Don't bother with the old interworking routines for Thumb-2. */ /* ??? Maybe only omit these on "m" variants. */ -#if !defined(__thumb2__) && !defined(__ARM_ARCH_6M__) +#if !defined(__thumb2__) && __ARM_ARCH_ISA_ARM #if defined L_interwork_call_via_rX @@ -1983,11 +1987,12 @@ LSYM(Lchange_\register): .endm #ifndef __symbian__ -#ifndef __ARM_ARCH_6M__ +/* The condition here must match the one in gcc/config/arm/elf.h. */ +#ifndef NOT_ISA_TARGET_32BIT #include "ieee754-df.S" #include "ieee754-sf.S" #include "bpabi.S" -#else /* __ARM_ARCH_6M__ */ +#else /* NOT_ISA_TARGET_32BIT */ #include "bpabi-v6m.S" -#endif /* __ARM_ARCH_6M__ */ +#endif /* NOT_ISA_TARGET_32BIT */ #endif /* !__symbian__ */ diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S index a68b10ddce93d230c504f3747dcad3832d9f753c..3d7e70181fa80fe53a4903c96bb0f90480feee21 100644 --- a/libgcc/config/arm/libunwind.S +++ b/libgcc/config/arm/libunwind.S @@ -58,7 +58,7 @@ #endif #endif -#ifdef __ARM_ARCH_6M__ +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1 /* r0 points to a 16-word block. Upload these values to the actual core state. */ @@ -169,7 +169,7 @@ FUNC_START gnu_Unwind_Save_WMMXC UNPREFIX \name .endm -#else /* !__ARM_ARCH_6M__ */ +#else /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */ /* r0 points to a 16-word block. Upload these values to the actual core state. */ @@ -351,7 +351,7 @@ ARM_FUNC_START gnu_Unwind_Save_WMMXC UNPREFIX \name .endm -#endif /* !__ARM_ARCH_6M__ */ +#endif /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != 1 */ UNWIND_WRAPPER _Unwind_RaiseException 1 UNWIND_WRAPPER _Unwind_Resume 1 diff --git a/libgcc/config/arm/t-softfp b/libgcc/config/arm/t-softfp index 4ede438baf6a297737e52db00395f6c3a359f681..554ec9bc47b04445e79e84b1f957bf88680c08d1 100644 --- a/libgcc/config/arm/t-softfp +++ b/libgcc/config/arm/t-softfp @@ -1,2 +1,2 @@ -softfp_wrap_start := '\#ifdef __ARM_ARCH_6M__' +softfp_wrap_start := '\#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB == 1' softfp_wrap_end := '\#endif'