From patchwork Tue May 31 15:51:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleg Endo X-Patchwork-Id: 628304 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rJyfM1t0Gz9t3Z for ; Wed, 1 Jun 2016 01:51:54 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=ngVRQK3p; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:date:content-type:mime-version; q= dns; s=default; b=Qin7xB1vm23vHSTkMZ2MAuSwyFwFG9Ov3yWqTLa8mN3I/z kCgiiKyJB4cDgEPWSUm5+Bc0x8h0GBNMzs/hnPj30z2bmmC31w4bRRQN9QBl4MKH 74u1g4Tm6A2ihy57o7az0yoM0GK5eOD0J35TaA2o3uHijaGKgM85btrAaMUto= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:date:content-type:mime-version; s= default; bh=hG/HQ253EG/gWs4Ah/0VEw/vac4=; b=ngVRQK3puu6PIHF3PWeV LVIqZhYJrYlV3lVrc956dR111J0KmyZmYovV0jo0e6R3YYCyiV4CG/EBQmticFp7 GzBsYCIDQcMVo58M0buJIYgCj0Pam5whLhPI/9gHmTGvvSqe5E5RJfhjheNRWe/j 2UcS7dteT1591hHcmIDVLJg= Received: (qmail 63443 invoked by alias); 31 May 2016 15:51:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 63410 invoked by uid 89); 31 May 2016 15:51:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.3 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Tell, sk:general, 869, RUNTESTFLAGS X-HELO: mailout08.t-online.de Received: from mailout08.t-online.de (HELO mailout08.t-online.de) (194.25.134.20) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Tue, 31 May 2016 15:51:33 +0000 Received: from fwd09.aul.t-online.de (fwd09.aul.t-online.de [172.20.27.151]) by mailout08.t-online.de (Postfix) with SMTP id 3F3E141D8BA0 for ; Tue, 31 May 2016 17:51:28 +0200 (CEST) Received: from [192.168.0.16] (GulRYcZd8hu+0WrS6IPGtCZboicoQlBOfJeEuTyPE69rzMNo-opAOvJZ99aN3fKZWx@[115.165.93.200]) by fwd09.t-online.de with (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384 encrypted) esmtp id 1b7lwz-3No2Yy0; Tue, 31 May 2016 17:51:25 +0200 Message-ID: <1464709883.15496.7.camel@t-online.de> Subject: =?ISO-8859-1?Q?=5BSH=5D=5Bcommitte=F0=5D?= Remove SH5 target regs leftovers From: Oleg Endo To: gcc-patches Date: Wed, 01 Jun 2016 00:51:23 +0900 Mime-Version: 1.0 X-IsSubscribed: yes Hi, The attached patch removes the SH5 target register leftovers. Tested on sh-elf with make -k check RUNTESTFLAGS="--target_board=sh-sim\{-m2/-ml,-m2/-mb, -m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}" Committed as r236928. Cheers, Oleg gcc/ChangeLog: * config/sh/constraints.md (b): Remove constraint. * config/sh/predicates.md (arith_reg_operand): Remove TARGET_REGISTER_P. * config/sh/sh-modes.def (PDI): Remove. * config/sh/sh.c (sh_target_reg_class, sh_optimize_target_register_callee_saved): Remove functions. (sh_option_override): Don't set MASK_SAVE_ALL_TARGET_REGS. (sh_expand_epilogue): Update comment. (sh_hard_regno_mode_ok, sh_register_move_cost, calc_live_regs, sh_secondary_reload): Remove TARGET_REGS related code. * config/sh/sh.h (FIRST_TARGET_REG, LAST_TARGET_REG, TARGET_REGISTER_P): Remove macros. (SH_DBX_REGISTER_NUMBER, REG_ALLOC_ORDER): Remove target regs. * config/sh/sh.md (PR_MEDIA_REG, T_MEDIA_REG, FR23_REG, TR0_REG, TR1_REG, TR2_REG): Remove constants. * config/sh/sh.opt (SAVE_ALL_TARGET_REGS): Remove. diff --git a/gcc/config/sh/constraints.md b/gcc/config/sh/constraints.md index 644a0f0..c3e9d55 100644 --- a/gcc/config/sh/constraints.md +++ b/gcc/config/sh/constraints.md @@ -62,9 +62,6 @@ (define_register_constraint "a" "ALL_REGS" "@internal") -(define_register_constraint "b" "TARGET_REGS" - "Branch target registers.") - (define_register_constraint "c" "FPSCR_REGS" "Floating-point status register.") diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md index 4de90af..4b93c6d 100644 --- a/gcc/config/sh/predicates.md +++ b/gcc/config/sh/predicates.md @@ -34,7 +34,6 @@ return 1; return (regno != T_REG && regno != PR_REG - && ! TARGET_REGISTER_P (regno) && regno != FPUL_REG && regno != FPSCR_REG && regno != MACH_REG && regno != MACL_REG); } diff --git a/gcc/config/sh/sh-modes.def b/gcc/config/sh/sh-modes.def index cab2011a..6db9943 100644 --- a/gcc/config/sh/sh-modes.def +++ b/gcc/config/sh/sh-modes.def @@ -17,9 +17,6 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see . */ -/* PDI mode is used to represent a function address in a target register. */ -PARTIAL_INT_MODE (DI, 64, PDI); - /* Vector modes. */ VECTOR_MODE (INT, QI, 2); /* V2QI */ VECTOR_MODES (INT, 4); /* V4QI V2HI */ diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index a36b098..2bd917a 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -234,8 +234,6 @@ static int sh_variable_issue (FILE *, int, rtx_insn *, int); static bool sh_function_ok_for_sibcall (tree, tree); static bool sh_can_follow_jump (const rtx_insn *, const rtx_insn *); -static reg_class_t sh_target_reg_class (void); -static bool sh_optimize_target_register_callee_saved (bool); static bool sh_ms_bitfield_layout_p (const_tree); static void sh_init_builtins (void); @@ -465,11 +463,6 @@ static const struct attribute_spec sh_attribute_table[] = #undef TARGET_CAN_FOLLOW_JUMP #define TARGET_CAN_FOLLOW_JUMP sh_can_follow_jump -#undef TARGET_BRANCH_TARGET_REGISTER_CLASS -#define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class -#undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED -#define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \ - sh_optimize_target_register_callee_saved #undef TARGET_MS_BITFIELD_LAYOUT_P #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p @@ -800,8 +793,6 @@ sh_option_override (void) int regno; SUBTARGET_OVERRIDE_OPTIONS; - if (optimize > 1 && !optimize_size) - target_flags |= MASK_SAVE_ALL_TARGET_REGS; sh_cpu = PROCESSOR_SH1; assembler_dialect = 0; @@ -7037,30 +7028,6 @@ calc_live_regs (HARD_REG_SET *live_regs_mask) if (nosave_low_regs && reg == R8_REG) break; } - /* If we have a target register optimization pass after prologue / epilogue - threading, we need to assume all target registers will be live even if - they aren't now. */ - if (flag_branch_target_load_optimize2 && TARGET_SAVE_ALL_TARGET_REGS) - for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--) - if ((! call_really_used_regs[reg] || interrupt_handler) - && ! TEST_HARD_REG_BIT (*live_regs_mask, reg)) - { - SET_HARD_REG_BIT (*live_regs_mask, reg); - count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg)); - } - /* If this is an interrupt handler, we don't have any call-clobbered - registers we can conveniently use for target register save/restore. - Make sure we save at least one general purpose register when we need - to save target registers. */ - if (interrupt_handler - && hard_reg_set_intersect_p (*live_regs_mask, - reg_class_contents[TARGET_REGS]) - && ! hard_reg_set_intersect_p (*live_regs_mask, - reg_class_contents[GENERAL_REGS])) - { - SET_HARD_REG_BIT (*live_regs_mask, R0_REG); - count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG)); - } return count; } @@ -7317,9 +7284,6 @@ sh_expand_epilogue (bool sibcall_p) emit_insn (gen_sp_switch_2 ()); /* Tell flow the insn that pops PR isn't dead. */ - /* PR_REG will never be live in SHmedia mode, and we don't need to - USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG - by the return pattern. */ if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)) emit_use (gen_rtx_REG (SImode, PR_REG)); } @@ -10014,19 +9978,6 @@ sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED, return 0; } -static reg_class_t -sh_target_reg_class (void) -{ - return NO_REGS; -} - -static bool -sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen - ATTRIBUTE_UNUSED) -{ - return false; -} - static bool sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED) { @@ -10582,9 +10533,6 @@ sh_hard_regno_mode_ok (unsigned int regno, machine_mode mode) if (XD_REGISTER_P (regno)) return mode == DFmode; - if (TARGET_REGISTER_P (regno)) - return (mode == DImode || mode == SImode || mode == PDImode); - if (regno == PR_REG) return mode == SImode; @@ -10726,10 +10674,6 @@ sh_register_move_cost (machine_mode mode, && (dstclass == PR_REGS || dstclass == MAC_REGS))) return 7; - if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass)) - || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass))) - return 20; - if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass)) || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass))) return 4; @@ -11324,17 +11268,11 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, return GENERAL_REGS; return NO_REGS; // LRA wants NO_REGS here, it used to be FPUL_REGS; } - if (rclass == TARGET_REGS - && !satisfies_constraint_Csy (x) - && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x)))) - return GENERAL_REGS; + if ((rclass == MAC_REGS || rclass == PR_REGS) && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x)) && rclass != REGNO_REG_CLASS (REGNO (x))) return GENERAL_REGS; - if (rclass != GENERAL_REGS && REG_P (x) - && TARGET_REGISTER_P (REGNO (x))) - return GENERAL_REGS; /* If here fall back to loading FPUL register through general registers. This case can happen when movsi_ie insn is picked initially to diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index a1a789f..d724bd2 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -585,8 +585,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ #define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)) #define FIRST_XD_REG XD0_REG #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1)) -#define FIRST_TARGET_REG TR0_REG -#define LAST_TARGET_REG (FIRST_TARGET_REG + (-1)) /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */ #define FIRST_BANKED_REG R0_REG @@ -623,9 +621,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ || (REGNO) == MACH_REG || (REGNO) == MACL_REG \ || (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG) -#define TARGET_REGISTER_P(REGNO) \ - ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG) - #define VALID_REGISTER_P(REGNO) \ (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ || XD_REGISTER_P (REGNO) \ @@ -1037,8 +1032,6 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; 44, 45, 46, 47, 48, 49, 50, 51, \ 52, 53, 54, 55, 56, 57, 58, 59, \ /* FPUL */ 150, \ - /* SH5 branch target registers */ \ - 128,129,130,131,132,133,134,135, \ /* Fixed registers */ \ 15, 16, 24, 25, 26, 27, 63,144, \ 145,146,147,148,149,152,153,154,155 } @@ -1698,13 +1691,6 @@ extern bool current_function_interrupt; register exists, so we should return -1 for invalid register numbers. */ #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO) -/* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers - used to use the encodings 245..260, but that doesn't make sense: - PR_REG and PR_MEDIA_REG are actually the same register, and likewise - the FP registers stay the same when switching between compact and media - mode. Hence, we also need to use the same dwarf frame columns. - Likewise, we need to support unwind information for SHmedia registers - even in compact code. */ #define SH_DBX_REGISTER_NUMBER(REGNO) \ (IN_RANGE ((REGNO), \ (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ @@ -1716,12 +1702,8 @@ extern bool current_function_interrupt; ? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \ : XD_REGISTER_P (REGNO) \ ? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \ - : TARGET_REGISTER_P (REGNO) \ - ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \ : (REGNO) == PR_REG \ ? (17) \ - : (REGNO) == PR_MEDIA_REG \ - ? ((unsigned) -1) \ : (REGNO) == GBR_REG \ ? (18) \ : (REGNO) == MACH_REG \ diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 30948ca..edc4d15 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -86,9 +86,6 @@ (FP_REG 14) (SP_REG 15) - (PR_MEDIA_REG 18) - (T_MEDIA_REG 19) - (R0_REG 0) (R1_REG 1) (R2_REG 2) @@ -108,11 +105,6 @@ (DR0_REG 64) (DR2_REG 66) (DR4_REG 68) - (FR23_REG 87) - - (TR0_REG 128) - (TR1_REG 129) - (TR2_REG 130) (XD0_REG 136) diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt index 2a94c9b..b348ee3 100644 --- a/gcc/config/sh/sh.opt +++ b/gcc/config/sh/sh.opt @@ -37,9 +37,6 @@ Mask(HARD_SH2A_DOUBLE) ;; Set if compiling for SH4 hardware (to be used for insn costs etc.) Mask(HARD_SH4) -;; Set if we should save all target registers. -Mask(SAVE_ALL_TARGET_REGS) - m1 Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1) Generate SH1 code.