From patchwork Wed May 4 07:31:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleg Endo X-Patchwork-Id: 618289 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r08qn75Cwz9t5w for ; Wed, 4 May 2016 17:31:47 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=n4URUiyi; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:date:content-type:mime-version; q= dns; s=default; b=FGqNqclGsOfLKmPYxtFhv6QU1NpQ60JEbKgmQBSr9yiaV9 9Mp1t7diq2nWazmlM/YXS277L58WsPRKxO2Ni+qPnj6Rs5jP1slRgZ+piOlZ90Yd Q7Kn5xBigV36ooxq5Vial4yXRzIqgRDBk23846rpH4u9YUm/qah10SXUb6qR0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:date:content-type:mime-version; s= default; bh=wdViPtTFLl9NuXnSfnQOV7p6cc4=; b=n4URUiyi1NmPRrChvZhV fCGBPJ0b/22nRhBoQcyDJS/Z4JlZyc3hMusypueYR2+MJ8AgAtcnIWEYbPzgCghB fChlt1AEn9Eh+LwRe1xTYGNkgvhlzTfJ3Bpy7nHzXiJPuP1TAU4WSc9Gdf23tjP1 HpwO+vsYVNetYWHs4qanIv4= Received: (qmail 17060 invoked by alias); 4 May 2016 07:31:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17051 invoked by uid 89); 4 May 2016 07:31:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.0 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=pre_dec, pressure X-HELO: mailout12.t-online.de Received: from mailout12.t-online.de (HELO mailout12.t-online.de) (194.25.134.22) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Wed, 04 May 2016 07:31:19 +0000 Received: from fwd27.aul.t-online.de (fwd27.aul.t-online.de [172.20.26.132]) by mailout12.t-online.de (Postfix) with SMTP id 1852E165ECF for ; Wed, 4 May 2016 09:31:15 +0200 (CEST) Received: from [192.168.0.16] (VmKJzkZlwhEvVD47YR0JQm6OSumX49hfZoR9jdI1k5RGytbCxme15BR8+kNWdyMQqe@[115.165.93.200]) by fwd27.t-online.de with (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384 encrypted) esmtp id 1axrH5-2R0bCK0; Wed, 4 May 2016 09:31:11 +0200 Message-ID: <1462347068.23746.9.camel@t-online.de> Subject: [SH][committed] Add support for additional SH2A post-inc/pre-dec addressing modes From: Oleg Endo To: gcc-patches Date: Wed, 04 May 2016 16:31:08 +0900 Mime-Version: 1.0 X-IsSubscribed: yes Hi, The attached patch adds support for the following SH2A addressing modes: mov.b @-Rm,R0 mov.w @-Rm,R0 mov.l @-Rm,R0 mov.b R0,@Rn+ mov.w R0,@Rn+ mov.l R0,@Rn+ The patch also tweaks the post-inc/pre-dec addressing mode usage on non -SH2A targets. CSiBE shows a total code size reduction of 1568 bytes ( -0.047074 %) for non-SH2A and a code size increase of +247 (+0.007505 %) for SH2A. The code size increase on SH2A is due to increased register usage/pressure. Where before displacement modes were used (reg + disp), it now tends to use post-inc stores. To do that, the address register (often the stack pointer) is often copied into another register first. Hopefully this issue can be improved later by the AMS optimization. Tested on sh-elf with make -k check RUNTESTFLAGS="--target_board=sh-sim\{-m2/-ml,-m2/-mb, -m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}" Committed as r235859. Cheers, Oleg gcc/ChangeLog: * config/sh/predicates (post_inc_mem, pre_dec_mem): New predicates. * config/sh/sh-protos.h (sh_find_set_of_reg): Return null result if result.set_rtx is null instead of aborting. * config/sh/sh.h (USE_LOAD_POST_INCREMENT, USE_STORE_PRE_DECREMENT): Always enable. (USE_LOAD_PRE_DECREMENT, USE_STORE_POST_INCREMENT): Enable for SH2A. * config/sh/sh.md (*extendsi2_predec, *mov_load_predec, *mov_store_postinc): New patterns. diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md index 3e69d88..b582637 100644 --- a/gcc/config/sh/predicates.md +++ b/gcc/config/sh/predicates.md @@ -230,6 +230,18 @@ (match_test "sh_disp_addr_displacement (op) <= sh_max_mov_insn_displacement (GET_MODE (op), false)"))) +;; Returns true if OP is a post-increment addressing mode memory reference. +(define_predicate "post_inc_mem" + (and (match_code "mem") + (match_code "post_inc" "0") + (match_code "reg" "00"))) + +;; Returns true if OP is a pre-decrement addressing mode memory reference. +(define_predicate "pre_dec_mem" + (and (match_code "mem") + (match_code "pre_dec" "0") + (match_code "reg" "00"))) + ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn. (define_predicate "zero_extend_movu_operand" (and (ior (match_operand 0 "displacement_mem_operand") diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h index ea7e847..c47e2ea 100644 --- a/gcc/config/sh/sh-protos.h +++ b/gcc/config/sh/sh-protos.h @@ -224,8 +224,12 @@ sh_find_set_of_reg (rtx reg, rtx_insn* insn, F stepfunc, } } - if (result.set_src != NULL) - gcc_assert (result.insn != NULL && result.set_rtx != NULL); + /* If the searched reg is found inside a (mem (post_inc:SI (reg))), set_of + will return NULL and set_rtx will be NULL. + In this case report a 'not found'. result.insn will always be non-null + at this point, so no need to check it. */ + if (result.set_src != NULL && result.set_rtx == NULL) + result.set_src = NULL; return result; } diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 60c6250..16b4a8e 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -1307,12 +1307,10 @@ struct sh_args { #define HAVE_POST_INCREMENT TARGET_SH1 #define HAVE_PRE_DECREMENT TARGET_SH1 -#define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \ - ? 0 : TARGET_SH1) -#define USE_LOAD_PRE_DECREMENT(mode) 0 -#define USE_STORE_POST_INCREMENT(mode) 0 -#define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \ - ? 0 : TARGET_SH1) +#define USE_LOAD_POST_INCREMENT(mode) TARGET_SH1 +#define USE_LOAD_PRE_DECREMENT(mode) TARGET_SH2A +#define USE_STORE_POST_INCREMENT(mode) TARGET_SH2A +#define USE_STORE_PRE_DECREMENT(mode) TARGET_SH1 /* If a memory clear move would take CLEAR_RATIO or more simple move-instruction pairs, we will do a setmem instead. */ diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 2d9502b..2a8fbc8 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -4820,6 +4820,15 @@ [(set_attr "type" "load") (set_attr "length" "2,2,4")]) +;; The pre-dec and post-inc mems must be captured by the '<' and '>' +;; constraints, otherwise wrong code might get generated. +(define_insn "*extendsi2_predec" + [(set (match_operand:SI 0 "arith_reg_dest" "=z") + (sign_extend:SI (match_operand:QIHI 1 "pre_dec_mem" "<")))] + "TARGET_SH2A" + "mov. %1,%0" + [(set_attr "type" "load")]) + ;; The *_snd patterns will take care of other QImode/HImode addressing ;; modes than displacement addressing. They must be defined _after_ the ;; displacement addressing patterns. Otherwise the displacement addressing @@ -5261,6 +5270,22 @@ prepare_move_operands (operands, mode); }) +;; The pre-dec and post-inc mems must be captured by the '<' and '>' +;; constraints, otherwise wrong code might get generated. +(define_insn "*mov_load_predec" + [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z") + (match_operand:QIHISI 1 "pre_dec_mem" "<"))] + "TARGET_SH2A" + "mov. %1,%0" + [(set_attr "type" "load")]) + +(define_insn "*mov_store_postinc" + [(set (match_operand:QIHISI 0 "post_inc_mem" "=>") + (match_operand:QIHISI 1 "arith_reg_operand" "z"))] + "TARGET_SH2A" + "mov. %1,%0" + [(set_attr "type" "store")]) + ;; Specifying the displacement addressing load / store patterns separately ;; before the generic movqi / movhi pattern allows controlling the order ;; in which load / store insns are selected in a more fine grained way.