From patchwork Sat Apr 30 05:44:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleg Endo X-Patchwork-Id: 617036 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qxffL72tHz9t3y for ; Sat, 30 Apr 2016 15:44:58 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=xRQBVtm0; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:date:in-reply-to:references :content-type:mime-version; q=dns; s=default; b=myyZTCaO9OoLc866 NA2Pmx7jWccmipNywWqBj+zno5YgswL81LcVrZcWaDvpGQkF9hdD7agLPiIFekaE 0GnNdIyf5gFX+3fuopyT8SFJstOPFEFIY64HZyenVTZNgswhG7/mSxet8mY4dhjo I+pINoBCtJfaZTYqppGsYL4Xndo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:date:in-reply-to:references :content-type:mime-version; s=default; bh=i7B/gqDkMWGRa9C4ffaN65 0zTB4=; b=xRQBVtm0j/kGTL+od/47iWsrIXz+bsUVWf0p1AY9AyWUT3Bkd3d+uk iKEc+7BZM3WK+AHaVnOxL997+8zLhPnREhI+ntR44traKvYrAOvcIC2wyxbZeG18 tCylsaoTqEcdKQSx0Nil1DJ5lOUOfJzdjfz2CeICcFtdc08f7xAeY= Received: (qmail 2522 invoked by alias); 30 Apr 2016 05:44:48 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 2432 invoked by uid 89); 30 Apr 2016 05:44:46 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.0 required=5.0 tests=AWL, BAYES_40, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=2016-04-30, GET_MODE_SIZE, get_mode_size, sk:first_p X-HELO: mailout04.t-online.de Received: from mailout04.t-online.de (HELO mailout04.t-online.de) (194.25.134.18) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sat, 30 Apr 2016 05:44:36 +0000 Received: from fwd19.aul.t-online.de (fwd19.aul.t-online.de [172.20.27.65]) by mailout04.t-online.de (Postfix) with SMTP id D6F4851F46 for ; Sat, 30 Apr 2016 07:44:31 +0200 (CEST) Received: from [192.168.0.16] (SsH5huZLwhzyRkUlgEX28tz8WMg8tYH49XMMGs9NNbPBu-m53INU7OLuvgA8ydAgKi@[115.165.93.200]) by fwd19.t-online.de with (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384 encrypted) esmtp id 1awNhe-2uTJ5c0; Sat, 30 Apr 2016 07:44:30 +0200 Message-ID: <1461995068.31604.54.camel@t-online.de> Subject: Re: [SH][committed] Remove SH5 support in compiler From: Oleg Endo To: gcc-patches Date: Sat, 30 Apr 2016 14:44:28 +0900 In-Reply-To: <1461981489.31604.46.camel@t-online.de> References: <1461806825.31604.5.camel@t-online.de> <1461926715.31604.28.camel@t-online.de> <1461939066.31604.38.camel@t-online.de> <1461981489.31604.46.camel@t-online.de> Mime-Version: 1.0 X-IsSubscribed: yes On Sat, 2016-04-30 at 10:58 +0900, Oleg Endo wrote: > On Fri, 2016-04-29 at 23:11 +0900, Oleg Endo wrote: > > On Fri, 2016-04-29 at 19:45 +0900, Oleg Endo wrote: > > > On Thu, 2016-04-28 at 10:27 +0900, Oleg Endo wrote: > > > > > > > The removal of SH5 support from GCC has been announced here > > > > https://gcc.gnu.org/ml/gcc/2015-08/msg00101.html > > > > > > > > The attached patch removes support for SH5 in the compiler back > > > > end. > > > > There are still some leftovers and new simplification > > > > opportunities. > > > > These will be addressed in later follow up patches. > > > > > > > > Tested on sh-elf with > > > > > > > > make -k check RUNTESTFLAGS="--target_board=sh-sim\{-m2/-ml,-m2/ > > > > -mb, > > > > -m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}" > > > > > > The attached patch removes some leftovers and reinstantes the > > > divsf3 > > > expander pattern which got accidentally deleted by the previous > > > patch. > > > > The attached patch removes SH5 support from libgcc. > > Tested as above. Committed as r235640. > > The attached patch removes SH5 checks in the testsuite. > Committed as r235673. The attached patch removes some remaining superfluous TARGET_SH1 checks. Tested with make -k check-gcc RUNTESTFLAGS="--target_board=sh-sim\{-m2/-ml,-m2/-mb, -m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"; Committed as r235674. Cheers, Oleg gcc/ChangeLog: * config/sh/sh.c (register_sh_passes, sh_option_override, sh_print_operand, prepare_move_operands, sh_can_follow_jump): Remove TARGET_SH1 checks. * config/sh/sh.h (TARGET_VARARGS_PRETEND_ARGS, VALID_REGISTER_P, PROMOTE_MODE): Likewise. * config/sh/sh.md (adddi3, addsi3, subdi3, subsi3, andsi3, movdi): Likewise. diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 3d9ce9d..b37d3ab 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -772,9 +772,6 @@ extern opt_pass* make_pass_sh_optimize_sett_clrt (gcc::context* ctx, static void register_sh_passes (void) { - if (!TARGET_SH1) - return; - /* Running the sh_treg_combine pass after ce1 generates better code when comparisons are combined and reg-reg moves are introduced, because reg-reg moves will be eliminated afterwards. However, there are quite @@ -848,36 +845,31 @@ sh_option_override (void) if (!TARGET_SH3 && TARGET_USERMODE) TARGET_USERMODE = false; - if (TARGET_SH1) + if (! strcmp (sh_div_str, "call-div1")) + sh_div_strategy = SH_DIV_CALL_DIV1; + else if (! strcmp (sh_div_str, "call-fp") && TARGET_FPU_ANY) + sh_div_strategy = SH_DIV_CALL_FP; + else if (! strcmp (sh_div_str, "call-table") && TARGET_DYNSHIFT) + sh_div_strategy = SH_DIV_CALL_TABLE; + else { - if (! strcmp (sh_div_str, "call-div1")) - sh_div_strategy = SH_DIV_CALL_DIV1; - else if (! strcmp (sh_div_str, "call-fp") - && (TARGET_FPU_DOUBLE || TARGET_FPU_SINGLE_ONLY - || TARGET_FPU_ANY)) - sh_div_strategy = SH_DIV_CALL_FP; - else if (! strcmp (sh_div_str, "call-table") && TARGET_DYNSHIFT) + /* Pick one that makes most sense for the target in general. + It is not much good to use different functions depending on -Os, + since then we'll end up with two different functions when some of + the code is compiled for size, and some for speed. */ + + /* SH4 tends to emphasize speed. */ + if (TARGET_HARD_SH4) sh_div_strategy = SH_DIV_CALL_TABLE; + /* These have their own way of doing things. */ + else if (TARGET_SH2A) + sh_div_strategy = SH_DIV_INTRINSIC; + /* SH1 .. SH3 cores often go into small-footprint systems, so + default to the smallest implementation available. */ else - /* Pick one that makes most sense for the target in general. - It is not much good to use different functions depending - on -Os, since then we'll end up with two different functions - when some of the code is compiled for size, and some for - speed. */ - - /* SH4 tends to emphasize speed. */ - if (TARGET_HARD_SH4) - sh_div_strategy = SH_DIV_CALL_TABLE; - /* These have their own way of doing things. */ - else if (TARGET_SH2A) - sh_div_strategy = SH_DIV_INTRINSIC; - /* SH1 .. SH3 cores often go into small-footprint systems, so - default to the smallest implementation available. */ - else - sh_div_strategy = SH_DIV_CALL_DIV1; + sh_div_strategy = SH_DIV_CALL_DIV1; } - if (!TARGET_SH1) - TARGET_PRETEND_CMOVE = 0; + if (sh_divsi3_libfunc[0]) ; /* User supplied - leave it alone. */ else if (TARGET_DIVIDE_CALL_FP) @@ -1443,8 +1435,7 @@ sh_print_operand (FILE *stream, rtx x, int code) break; default: - if (TARGET_SH1) - fputc ('#', stream); + fputc ('#', stream); output_addr_const (stream, x); break; } @@ -1618,8 +1609,7 @@ prepare_move_operands (rtx operands[], machine_mode mode) of a library call to the target. Reject `st r0,@(rX,rY)' because reload will fail to find a spill register for rX, since r0 is already being used for the source. */ - else if (TARGET_SH1 - && refers_to_regno_p (R0_REG, operands[1]) + else if (refers_to_regno_p (R0_REG, operands[1]) && MEM_P (operands[0]) && GET_CODE (XEXP (operands[0], 0)) == PLUS && REG_P (XEXP (XEXP (operands[0], 0), 1))) @@ -1639,7 +1629,7 @@ prepare_move_operands (rtx operands[], machine_mode mode) case. We can pre-allocate R0 for that index term to avoid the issue. See PR target/66591. */ else if (sh_lra_p () - && TARGET_SH1 && ! TARGET_SH2A + && ! TARGET_SH2A && ((REG_P (operands[0]) && MEM_P (operands[1])) || (REG_P (operands[1]) && MEM_P (operands[0])))) { @@ -9590,8 +9580,7 @@ sh_can_follow_jump (const rtx_insn *branch1, const rtx_insn *branch2) { /* Don't follow if BRANCH2 is possible to be a jump crossing between hot and cold partitions. */ - if (TARGET_SH1 - && flag_reorder_blocks_and_partition + if (flag_reorder_blocks_and_partition && simplejump_p (branch2) && CROSSING_JUMP_P (branch2)) return false; diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 9f104f0..31d75e8 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -77,7 +77,7 @@ extern int code_for_indirect_jump_scratch; /* This is not used by the SH2E calling convention */ #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \ - (TARGET_SH1 && ! TARGET_SH2E \ + (! TARGET_SH2E \ && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL))) #ifndef TARGET_CPU_DEFAULT @@ -636,7 +636,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ || XD_REGISTER_P (REGNO) \ || (REGNO) == AP_REG || (REGNO) == RAP_REG \ || (REGNO) == FRAME_POINTER_REGNUM \ - || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ + || ((SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ || (TARGET_SH2E && (REGNO) == FPUL_REG)) /* The mode that should be generally used to store a register by @@ -1879,8 +1879,7 @@ extern int current_function_interrupt; #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ if (GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\ - (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \ - (MODE) = (TARGET_SH1 ? SImode : DImode); + (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), (MODE) = SImode; #define MAX_FIXED_MODE_SIZE (64) diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index ef90303..ad29426 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -1529,12 +1529,9 @@ (match_operand:DI 2 "arith_operand")))] "" { - if (TARGET_SH1) - { - operands[2] = force_reg (DImode, operands[2]); - emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2])); - DONE; - } + operands[2] = force_reg (DImode, operands[2]); + emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2])); + DONE; }) (define_insn_and_split "adddi3_compact" @@ -1780,7 +1777,7 @@ (match_operand:SI 2 "arith_or_int_operand")))] "" { - if (TARGET_SH1 && !arith_operand (operands[2], SImode)) + if (!arith_operand (operands[2], SImode)) { if (!sh_lra_p () || reg_overlap_mentioned_p (operands[0], operands[1])) { @@ -1935,12 +1932,9 @@ (match_operand:DI 2 "arith_reg_operand" "")))] "" { - if (TARGET_SH1) - { - operands[1] = force_reg (DImode, operands[1]); - emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2])); - DONE; - } + operands[1] = force_reg (DImode, operands[1]); + emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2])); + DONE; }) (define_insn_and_split "subdi3_compact" @@ -2165,7 +2159,7 @@ (match_operand:SI 2 "arith_reg_operand" "")))] "" { - if (TARGET_SH1 && CONST_INT_P (operands[1])) + if (CONST_INT_P (operands[1])) { emit_insn (gen_negsi2 (operands[0], operands[2])); emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); @@ -2840,20 +2834,18 @@ Ideally the splitter of *andsi_compact would be enough, if redundant zero extensions were detected after the combine pass, which does not happen at the moment. */ - if (TARGET_SH1) + + if (satisfies_constraint_Jmb (operands[2])) { - if (satisfies_constraint_Jmb (operands[2])) - { - emit_insn (gen_zero_extendqisi2 (operands[0], - gen_lowpart (QImode, operands[1]))); - DONE; - } - else if (satisfies_constraint_Jmw (operands[2])) - { - emit_insn (gen_zero_extendhisi2 (operands[0], - gen_lowpart (HImode, operands[1]))); - DONE; - } + emit_insn (gen_zero_extendqisi2 (operands[0], + gen_lowpart (QImode, operands[1]))); + DONE; + } + else if (satisfies_constraint_Jmw (operands[2])) + { + emit_insn (gen_zero_extendhisi2 (operands[0], + gen_lowpart (HImode, operands[1]))); + DONE; } }) @@ -5565,23 +5557,19 @@ "" { prepare_move_operands (operands, DImode); - if (TARGET_SH1) - { - /* When the dest operand is (R0, R1) register pair, split it to - two movsi of which dest is R1 and R0 so as to lower R0-register - pressure on the first movsi. Apply only for simple source not - to make complex rtl here. */ - if (REG_P (operands[0]) - && REGNO (operands[0]) == R0_REG - && REG_P (operands[1]) - && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) - { - emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG), - gen_rtx_SUBREG (SImode, operands[1], 4))); - emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG), - gen_rtx_SUBREG (SImode, operands[1], 0))); - DONE; - } + + /* When the dest operand is (R0, R1) register pair, split it to + two movsi of which dest is R1 and R0 so as to lower R0-register + pressure on the first movsi. Apply only for simple source not + to make complex rtl here. */ + if (REG_P (operands[0]) && REGNO (operands[0]) == R0_REG + && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) + { + emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG), + gen_rtx_SUBREG (SImode, operands[1], 4))); + emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG), + gen_rtx_SUBREG (SImode, operands[1], 0))); + DONE; } })