[SH,committed] Remove SH5 support in compiler

diff --git a/gcc/testsuite/g++.old-deja/g++.jason/thunk3.C b/gcc/testsuite/g++.old-deja/g++.jason/thunk3.C
index 7e0b93a..5ea46f5 100644
--- a/gcc/testsuite/g++.old-deja/g++.jason/thunk3.C
+++ b/gcc/testsuite/g++.old-deja/g++.jason/thunk3.C
@@ -1,5 +1,5 @@ 
 // { dg-do run }
-// { dg-skip-if "fails with generic thunk support" { rs6000-*-* powerpc-*-eabi v850-*-* sh-*-* sh64-*-* h8*-*-* xtensa*-*-* m32r*-*-* lm32-*-* nios2-*-* } { "*" } { "" } }
+// { dg-skip-if "fails with generic thunk support" { rs6000-*-* powerpc-*-eabi v850-*-* sh-*-* h8*-*-* xtensa*-*-* m32r*-*-* lm32-*-* nios2-*-* } { "*" } { "" } }
 // Test that variadic function calls using thunks work right.
 // Note that this will break on any target that uses the generic thunk
 //  support, because it doesn't support variadic functions.
diff --git a/gcc/testsuite/gcc.dg/20021029-1.c b/gcc/testsuite/gcc.dg/20021029-1.c
index 9da8e81..f11a6e4 100644
--- a/gcc/testsuite/gcc.dg/20021029-1.c
+++ b/gcc/testsuite/gcc.dg/20021029-1.c
@@ -2,7 +2,6 @@ 
    variables into writable sections.  */
 /* { dg-do compile { target fpic } } */
 /* { dg-options "-O2 -fpic" } */
-/* { dg-options "-O2 -fpic -mpt-fixed" { target sh64*-*-* } } */
 /* { dg-final { scan-assembler-not ".data.rel.ro.local" } } */
 /* { dg-require-effective-target label_values } */
 /* { dg-require-effective-target indirect_jumps } */
diff --git a/gcc/testsuite/gcc.target/sh/attr-isr-trap_exit.c b/gcc/testsuite/gcc.target/sh/attr-isr-trap_exit.c
index a45e92f..6c63ebf 100644
--- a/gcc/testsuite/gcc.target/sh/attr-isr-trap_exit.c
+++ b/gcc/testsuite/gcc.target/sh/attr-isr-trap_exit.c
@@ -1,7 +1,6 @@ 
 /* Check that trapa / interrput_handler attributes can paired in
    either order.  */
 /* { dg-do compile }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-options "-O" }  */
 /* { dg-final { scan-assembler "trapa\[ \t\]\[ \t\]*#4"} }  */
 /* { dg-final { scan-assembler-times "trapa" 1 } }  */
diff --git a/gcc/testsuite/gcc.target/sh/attr-isr-trapa.c b/gcc/testsuite/gcc.target/sh/attr-isr-trapa.c
index 3f850ac..a0c45bb 100644
--- a/gcc/testsuite/gcc.target/sh/attr-isr-trapa.c
+++ b/gcc/testsuite/gcc.target/sh/attr-isr-trapa.c
@@ -1,6 +1,5 @@ 
 /* Check that no interrupt-specific register saves are generated.  */
 /* { dg-do compile { target { { "sh*-*-*" } && nonpic } } }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-options "-O" }  */
 /* { dg-final { scan-assembler-times "rte" 1 } }  */
 /* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } }  */
diff --git a/gcc/testsuite/gcc.target/sh/cmpstr.c b/gcc/testsuite/gcc.target/sh/cmpstr.c
index 1b45089..e8f1de7 100644
--- a/gcc/testsuite/gcc.target/sh/cmpstr.c
+++ b/gcc/testsuite/gcc.target/sh/cmpstr.c
@@ -2,7 +2,6 @@ 
    when optimizing for speed.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "jmp" } } */
 /* { dg-final { scan-assembler-times "cmp/str" 3 } } */
 /* { dg-final { scan-assembler-times "tst\t#3" 2 } } */
diff --git a/gcc/testsuite/gcc.target/sh/cmpstrn.c b/gcc/testsuite/gcc.target/sh/cmpstrn.c
index 65cb9d6..6dd1151 100644
--- a/gcc/testsuite/gcc.target/sh/cmpstrn.c
+++ b/gcc/testsuite/gcc.target/sh/cmpstrn.c
@@ -2,7 +2,6 @@ 
    when optimizing for speed.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "jmp" } } */
 /* { dg-final { scan-assembler-times "cmp/str" 1 } } */
 
diff --git a/gcc/testsuite/gcc.target/sh/memset.c b/gcc/testsuite/gcc.target/sh/memset.c
index 4695db3..e888d1d 100644
--- a/gcc/testsuite/gcc.target/sh/memset.c
+++ b/gcc/testsuite/gcc.target/sh/memset.c
@@ -2,7 +2,6 @@ 
    optimizing for speed.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "jmp" } } */
 
 void
diff --git a/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c b/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c
index 531ed39..b9063de 100644
--- a/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c
+++ b/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c
@@ -1,5 +1,5 @@ 
-/* { dg-do compile }  */
-/* { dg-options "-mb -O2 -fomit-frame-pointer" } */
+/* { dg-do compile { target { big_endian } } }  */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
 /* { dg-final { scan-assembler "mov @r.,r.; mov @\\(4,r.\\),r." } } */
 double d;
 
@@ -10,10 +10,6 @@  f (void)
 
 /* If -ml from the target options is passed after -mb from dg-options, we
    end up with th reverse endianness.  */
-#if TARGET_SHMEDIA || defined (__LITTLE_ENDIAN__)
-  asm ("mov @r1,r3; mov @(4,r1),r4");
-#else
   asm ("mov %S1,%S0; mov %R1,%R0" : "=&r" (r) : "m" (d));
-#endif
   return r;
 }
diff --git a/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c b/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c
index 6948f47..10412f1 100644
--- a/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c
+++ b/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c
@@ -1,6 +1,5 @@ 
-/* { dg-do compile }  */
+/* { dg-do compile { target { little_endian } } }  */
 /* { dg-options "-O2 -fomit-frame-pointer" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-mb" && "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler "mov @\\(4,r.\\),r.; mov @r.,r." } } */
 double d;
 
diff --git a/gcc/testsuite/gcc.target/sh/pr39423-1.c b/gcc/testsuite/gcc.target/sh/pr39423-1.c
index 1e02937..8bf87b5 100644
--- a/gcc/testsuite/gcc.target/sh/pr39423-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr39423-1.c
@@ -2,7 +2,6 @@ 
    small offset, instead of re-calculating the index.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "add\t#1" } } */
 
 int
diff --git a/gcc/testsuite/gcc.target/sh/pr49468-di.c b/gcc/testsuite/gcc.target/sh/pr49468-di.c
index 4b17fce..6f6611f 100644
--- a/gcc/testsuite/gcc.target/sh/pr49468-di.c
+++ b/gcc/testsuite/gcc.target/sh/pr49468-di.c
@@ -2,7 +2,6 @@ 
    and conditional branch instead of default branch-free code.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "negc" 4 } } */
 
 
diff --git a/gcc/testsuite/gcc.target/sh/pr49468-si.c b/gcc/testsuite/gcc.target/sh/pr49468-si.c
index 8c771ed..2b25920 100644
--- a/gcc/testsuite/gcc.target/sh/pr49468-si.c
+++ b/gcc/testsuite/gcc.target/sh/pr49468-si.c
@@ -2,7 +2,6 @@ 
    conditional branch instead of default branch-free code.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "neg" 2 } } */
 
 
diff --git a/gcc/testsuite/gcc.target/sh/pr49880-1.c b/gcc/testsuite/gcc.target/sh/pr49880-1.c
index 249fae0..db30875 100644
--- a/gcc/testsuite/gcc.target/sh/pr49880-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr49880-1.c
@@ -1,7 +1,6 @@ 
 /* Check that the option -mdiv=call-div1 works.  */
 /* { dg-do link }  */
 /* { dg-options "-mdiv=call-div1" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 
 int
 test00 (int a, int b)
diff --git a/gcc/testsuite/gcc.target/sh/pr49880-2.c b/gcc/testsuite/gcc.target/sh/pr49880-2.c
index 35e23de..193b95c 100644
--- a/gcc/testsuite/gcc.target/sh/pr49880-2.c
+++ b/gcc/testsuite/gcc.target/sh/pr49880-2.c
@@ -1,7 +1,6 @@ 
 /* Check that the option -mdiv=call-fp works.  */
 /* { dg-do link }  */
 /* { dg-options "-mdiv=call-fp" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 
 int
 test00 (int a, int b)
diff --git a/gcc/testsuite/gcc.target/sh/pr49880-3.c b/gcc/testsuite/gcc.target/sh/pr49880-3.c
index be6ea52..dd4f9b2 100644
--- a/gcc/testsuite/gcc.target/sh/pr49880-3.c
+++ b/gcc/testsuite/gcc.target/sh/pr49880-3.c
@@ -1,7 +1,6 @@ 
 /* Check that the option -mdiv=call-table works.  */
 /* { dg-do link }  */
 /* { dg-options "-mdiv=call-table" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 
 int
 test00 (int a, int b)
diff --git a/gcc/testsuite/gcc.target/sh/pr50751-1.c b/gcc/testsuite/gcc.target/sh/pr50751-1.c
index 80c63fb..d4a3c86 100644
--- a/gcc/testsuite/gcc.target/sh/pr50751-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr50751-1.c
@@ -3,7 +3,6 @@ 
    calculations outside the mov insns.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "add|sub" } } */
 
 void
diff --git a/gcc/testsuite/gcc.target/sh/pr50751-4.c b/gcc/testsuite/gcc.target/sh/pr50751-4.c
index e0f3ab7..492ceff 100644
--- a/gcc/testsuite/gcc.target/sh/pr50751-4.c
+++ b/gcc/testsuite/gcc.target/sh/pr50751-4.c
@@ -3,7 +3,6 @@ 
    calculations outside the mov insns.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "add|sub" } } */
 
 void
diff --git a/gcc/testsuite/gcc.target/sh/pr50751-7.c b/gcc/testsuite/gcc.target/sh/pr50751-7.c
index 014575a..9aa84b3 100644
--- a/gcc/testsuite/gcc.target/sh/pr50751-7.c
+++ b/gcc/testsuite/gcc.target/sh/pr50751-7.c
@@ -3,7 +3,6 @@ 
    outside the mov insns.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "add|sub" } } */
 
 typedef struct 
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-1.c b/gcc/testsuite/gcc.target/sh/pr51244-1.c
index 15e2ebd..1da824d 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-1.c
@@ -3,7 +3,6 @@ 
    test instructions.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1 -mbranch-cost=2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "movt|tst|negc|extu" } } */
 
 int
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-10.c b/gcc/testsuite/gcc.target/sh/pr51244-10.c
index ef16b75..bbbd813 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-10.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-10.c
@@ -12,7 +12,6 @@ 
 */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "shll|subc|and" } } */
 int
 test_00 (int* p)
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-11.c b/gcc/testsuite/gcc.target/sh/pr51244-11.c
index b673e9a..fea7f6c 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-11.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-11.c
@@ -2,7 +2,6 @@ 
    execution patterns.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1 -mzdcbranch" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "subc|and" } } */
 
 int*
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-12.c b/gcc/testsuite/gcc.target/sh/pr51244-12.c
index 027c5ab..f0c62e6 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-12.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-12.c
@@ -3,7 +3,6 @@ 
    which handles the inverted case does not work properly.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 
 /* { dg-final { scan-assembler-times "negc" 15 { target { ! sh2a } } } } */
 /* { dg-final { scan-assembler-times "addc" 3 { target { ! sh2a } } } } */
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-13.c b/gcc/testsuite/gcc.target/sh/pr51244-13.c
index f9a851d..04937e6 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-13.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-13.c
@@ -10,7 +10,6 @@ 
    insns.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-times "tst" 2 } } */
 
 void printk (const char*, const char*, int);
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-14.c b/gcc/testsuite/gcc.target/sh/pr51244-14.c
index 61a5dc93..70d6893 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-14.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-14.c
@@ -12,7 +12,6 @@ 
    patterns, we only check for the extu.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "extu" } } */
 
 typedef struct transaction_s transaction_t;
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-17.c b/gcc/testsuite/gcc.target/sh/pr51244-17.c
index 621abb7..06c77cd 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-17.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-17.c
@@ -2,7 +2,6 @@ 
    results of arithmetic with T bit inputs.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "extu|exts" } } */
 
 int
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-18.c b/gcc/testsuite/gcc.target/sh/pr51244-18.c
index 19b244c..93dbcac 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-18.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-18.c
@@ -14,7 +14,6 @@ 
    reload.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "movt|tst" } } */
 
 typedef char Char;
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-19.c b/gcc/testsuite/gcc.target/sh/pr51244-19.c
index 5845d93..328099d 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-19.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-19.c
@@ -25,7 +25,6 @@ 
    reload.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "movt" } } */
 
 struct request
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-4.c b/gcc/testsuite/gcc.target/sh/pr51244-4.c
index ac967bf..9d9361c 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-4.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-4.c
@@ -2,7 +2,6 @@ 
    uses the subc instruction.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1 -mbranch-cost=2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-not "movt|tst|negc|movrt" } } */
 /* { dg-final { scan-assembler-times "subc" 3 } }  */
 /* { dg-final { scan-assembler-times "not\t" 1 } }  */
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-5.c b/gcc/testsuite/gcc.target/sh/pr51244-5.c
index c0f05a1..4c7d5bf 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-5.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-5.c
@@ -2,7 +2,6 @@ 
    a negc or movrt insn that stores the inverted T bit in a reg.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "extu|exts" } } */
 
 int
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-7.c b/gcc/testsuite/gcc.target/sh/pr51244-7.c
index d4d3974..69f890d 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-7.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-7.c
@@ -12,7 +12,6 @@ 
 */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "cmp/hi" } } */
 /* { dg-final { scan-assembler-not "mov\t#0" } } */
 
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-8.c b/gcc/testsuite/gcc.target/sh/pr51244-8.c
index d8c1269..fbd948b 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-8.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-8.c
@@ -8,7 +8,6 @@ 
 */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "shad|neg" } } */
 
 int test_01_00 (int*, void*);
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-9.c b/gcc/testsuite/gcc.target/sh/pr51244-9.c
index cca90a8..af8a465 100644
--- a/gcc/testsuite/gcc.target/sh/pr51244-9.c
+++ b/gcc/testsuite/gcc.target/sh/pr51244-9.c
@@ -10,7 +10,6 @@ 
 */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "mov\t#0" } } */
 static inline unsigned int
 test_03_00 (unsigned int x)
diff --git a/gcc/testsuite/gcc.target/sh/pr51697.c b/gcc/testsuite/gcc.target/sh/pr51697.c
index d63e329..0107e29 100644
--- a/gcc/testsuite/gcc.target/sh/pr51697.c
+++ b/gcc/testsuite/gcc.target/sh/pr51697.c
@@ -2,7 +2,6 @@ 
    with -Os.  */
 /* { dg-do compile }  */
 /* { dg-options "-Os" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "tst" 2 } }  */
 /* { dg-final { scan-assembler-not "cmp" } }  */
 
diff --git a/gcc/testsuite/gcc.target/sh/pr52483-1.c b/gcc/testsuite/gcc.target/sh/pr52483-1.c
index ca64a0a..7a1c202 100644
--- a/gcc/testsuite/gcc.target/sh/pr52483-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr52483-1.c
@@ -2,7 +2,6 @@ 
    sign/zero extensions.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-not "exts|extu" } } */
 
 int
diff --git a/gcc/testsuite/gcc.target/sh/pr52483-2.c b/gcc/testsuite/gcc.target/sh/pr52483-2.c
index 68e7f8e..91b485e 100644
--- a/gcc/testsuite/gcc.target/sh/pr52483-2.c
+++ b/gcc/testsuite/gcc.target/sh/pr52483-2.c
@@ -2,7 +2,6 @@ 
    addressing modes and do not result in redundant sign/zero extensions. */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "@\\(5," 4 } } */
 /* { dg-final { scan-assembler-times "@\\(10," 4 } } */
 /* { dg-final { scan-assembler-times "@\\(20," 4 } } */
diff --git a/gcc/testsuite/gcc.target/sh/pr52483-3.c b/gcc/testsuite/gcc.target/sh/pr52483-3.c
index baeec33..e0a02e0 100644
--- a/gcc/testsuite/gcc.target/sh/pr52483-3.c
+++ b/gcc/testsuite/gcc.target/sh/pr52483-3.c
@@ -2,7 +2,6 @@ 
    modes and do not result in redundant sign/zero extensions. */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "@\\(r0," 6 } } */
 /* { dg-final { scan-assembler-not "exts|extu" } } */
 
diff --git a/gcc/testsuite/gcc.target/sh/pr52483-5.c b/gcc/testsuite/gcc.target/sh/pr52483-5.c
index 50aefe2..947e8df 100644
--- a/gcc/testsuite/gcc.target/sh/pr52483-5.c
+++ b/gcc/testsuite/gcc.target/sh/pr52483-5.c
@@ -2,7 +2,6 @@ 
    modes and do not result in redundant sign extensions. */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "@r\[0-9\]\+\\+," 3 } } */
 /* { dg-final { scan-assembler-not "exts" } } */
 
diff --git a/gcc/testsuite/gcc.target/sh/pr52933-1.c b/gcc/testsuite/gcc.target/sh/pr52933-1.c
index 0c69027..138de7f 100644
--- a/gcc/testsuite/gcc.target/sh/pr52933-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr52933-1.c
@@ -4,7 +4,6 @@ 
    logic usually show up as redundant tst insns.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-times "div0s" 32 } } */
 /* { dg-final { scan-assembler-not "tst" } } */
 /* { dg-final { scan-assembler-not "not\t" } }  */
diff --git a/gcc/testsuite/gcc.target/sh/pr52933-2.c b/gcc/testsuite/gcc.target/sh/pr52933-2.c
index 67e2753..4637f0e 100644
--- a/gcc/testsuite/gcc.target/sh/pr52933-2.c
+++ b/gcc/testsuite/gcc.target/sh/pr52933-2.c
@@ -5,7 +5,6 @@ 
    logic usually show up as redundant tst insns.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2 -mpretend-cmove" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-times "div0s" 32 } } */
 /* { dg-final { scan-assembler-not "tst" } } */
 /* { dg-final { scan-assembler-not "not\t" } }  */
diff --git a/gcc/testsuite/gcc.target/sh/pr52933-3.c b/gcc/testsuite/gcc.target/sh/pr52933-3.c
index fadcc9e..1b563fe 100644
--- a/gcc/testsuite/gcc.target/sh/pr52933-3.c
+++ b/gcc/testsuite/gcc.target/sh/pr52933-3.c
@@ -1,7 +1,6 @@ 
 /* Check that the div0s instruction is used for integer sign comparisons.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-times "div0s" 2 } } */
 
 typedef struct { unsigned int arg[100]; } *FunctionCallInfo;
diff --git a/gcc/testsuite/gcc.target/sh/pr53568-1.c b/gcc/testsuite/gcc.target/sh/pr53568-1.c
index e274170..673d0a1 100644
--- a/gcc/testsuite/gcc.target/sh/pr53568-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr53568-1.c
@@ -2,7 +2,6 @@ 
    instructions.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "swap.w" 7 } } */
 /* { dg-final { scan-assembler-times "swap.b" 16 } } */
 /* { dg-final { scan-assembler-times "extu.w" 2 } } */
diff --git a/gcc/testsuite/gcc.target/sh/pr53976-1.c b/gcc/testsuite/gcc.target/sh/pr53976-1.c
index 68f8cdc..716a009 100644
--- a/gcc/testsuite/gcc.target/sh/pr53976-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr53976-1.c
@@ -2,7 +2,6 @@ 
    works as expected.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-times "clrt" 2 } } */
 /* { dg-final { scan-assembler-times "sett" 1 } } */
 
diff --git a/gcc/testsuite/gcc.target/sh/pr53988-1.c b/gcc/testsuite/gcc.target/sh/pr53988-1.c
index 4e0d49e..4db7b70 100644
--- a/gcc/testsuite/gcc.target/sh/pr53988-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr53988-1.c
@@ -2,7 +2,6 @@ 
    tst Rm,Rn instruction is used.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "tst\tr" 8 } }  */
 /* { dg-final { scan-assembler-times "mov.b" 4 } }  */
 /* { dg-final { scan-assembler-times "mov.w" 4 } }  */
diff --git a/gcc/testsuite/gcc.target/sh/pr53988.c b/gcc/testsuite/gcc.target/sh/pr53988.c
index a2e7213..3e21351 100644
--- a/gcc/testsuite/gcc.target/sh/pr53988.c
+++ b/gcc/testsuite/gcc.target/sh/pr53988.c
@@ -4,7 +4,6 @@ 
    movu insn.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "tst\tr" 8 } } */
 /* { dg-final { scan-assembler-not "tst\t#255" } } */
 /* { dg-final { scan-assembler-not "exts|extu|and|movu" } } */
diff --git a/gcc/testsuite/gcc.target/sh/pr54089-1.c b/gcc/testsuite/gcc.target/sh/pr54089-1.c
index 418ba69..64f79eb 100644
--- a/gcc/testsuite/gcc.target/sh/pr54089-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr54089-1.c
@@ -1,7 +1,6 @@ 
 /* Check that the rotcr instruction is generated.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "rotcr" 24 } } */
 /* { dg-final { scan-assembler-times "shll\t" 1 } } */
 /* { dg-final { scan-assembler-not "and\t#1" } }  */
diff --git a/gcc/testsuite/gcc.target/sh/pr54089-6.c b/gcc/testsuite/gcc.target/sh/pr54089-6.c
index 577690d..e8daa29 100644
--- a/gcc/testsuite/gcc.target/sh/pr54089-6.c
+++ b/gcc/testsuite/gcc.target/sh/pr54089-6.c
@@ -1,7 +1,6 @@ 
 /* Check that the rotr and rotl instructions are generated.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "rotr" 2 } } */
 /* { dg-final { scan-assembler-times "rotl" 3 } } */
 
diff --git a/gcc/testsuite/gcc.target/sh/pr54089-7.c b/gcc/testsuite/gcc.target/sh/pr54089-7.c
index 0476f75..b302364 100644
--- a/gcc/testsuite/gcc.target/sh/pr54089-7.c
+++ b/gcc/testsuite/gcc.target/sh/pr54089-7.c
@@ -1,7 +1,6 @@ 
 /* Check that the rotcr instruction is generated.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "rotcr" 4 } } */
 /* { dg-final { scan-assembler-not "movt" } } */
 /* { dg-final { scan-assembler-not "or\t" } } */
diff --git a/gcc/testsuite/gcc.target/sh/pr54089-8.c b/gcc/testsuite/gcc.target/sh/pr54089-8.c
index 20b0098..6af1750 100644
--- a/gcc/testsuite/gcc.target/sh/pr54089-8.c
+++ b/gcc/testsuite/gcc.target/sh/pr54089-8.c
@@ -1,7 +1,6 @@ 
 /* Check that the rotcl instruction is generated.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "rotcl" 28 } } */
 
 typedef char bool;
diff --git a/gcc/testsuite/gcc.target/sh/pr54089-9.c b/gcc/testsuite/gcc.target/sh/pr54089-9.c
index 8aa15df..3ced51e 100644
--- a/gcc/testsuite/gcc.target/sh/pr54089-9.c
+++ b/gcc/testsuite/gcc.target/sh/pr54089-9.c
@@ -1,7 +1,6 @@ 
 /* Check that the rotcr instruction is generated.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "rotcl" 4 } } */
 /* { dg-final { scan-assembler-not "movt" } } */
 /* { dg-final { scan-assembler-not "or\t" } } */
diff --git a/gcc/testsuite/gcc.target/sh/pr54236-1.c b/gcc/testsuite/gcc.target/sh/pr54236-1.c
index 31008ca..0b52a6a 100644
--- a/gcc/testsuite/gcc.target/sh/pr54236-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr54236-1.c
@@ -3,7 +3,7 @@ 
    movt instructions in these cases.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+
 /* { dg-final { scan-assembler-times "addc" 6 } } */
 /* { dg-final { scan-assembler-times "subc" 4 } } */
 /* { dg-final { scan-assembler-times "sett" 5 } } */
diff --git a/gcc/testsuite/gcc.target/sh/pr54236-2.c b/gcc/testsuite/gcc.target/sh/pr54236-2.c
index b6c2493..1e2f3bb 100644
--- a/gcc/testsuite/gcc.target/sh/pr54236-2.c
+++ b/gcc/testsuite/gcc.target/sh/pr54236-2.c
@@ -3,7 +3,7 @@ 
    these cases.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+
 /* { dg-final { scan-assembler-times "addc" 36 } } */
 /* { dg-final { scan-assembler-times "shll" 14 } } */
 /* { dg-final { scan-assembler-times "add\tr" 12 } } */
diff --git a/gcc/testsuite/gcc.target/sh/pr54236-3.c b/gcc/testsuite/gcc.target/sh/pr54236-3.c
index 933ece3..cd3d353 100644
--- a/gcc/testsuite/gcc.target/sh/pr54236-3.c
+++ b/gcc/testsuite/gcc.target/sh/pr54236-3.c
@@ -3,7 +3,6 @@ 
    these cases.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
 /* { dg-final { scan-assembler-times "addc" 4 } }  */
 /* { dg-final { scan-assembler-times "subc" 5 } }  */
 /* { dg-final { scan-assembler-times "movt" 1 } }  */
diff --git a/gcc/testsuite/gcc.target/sh/pr54236-4.c b/gcc/testsuite/gcc.target/sh/pr54236-4.c
index dce413e..4a3ffd1 100644
--- a/gcc/testsuite/gcc.target/sh/pr54236-4.c
+++ b/gcc/testsuite/gcc.target/sh/pr54236-4.c
@@ -2,7 +2,7 @@ 
    inverted.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+
 /* { dg-final { scan-assembler-times "cmp/eq" 7 } }  */
 
 /* { dg-final { scan-assembler-times "subc" 5 { target { ! sh2a } } } }  */
diff --git a/gcc/testsuite/gcc.target/sh/pr54386.c b/gcc/testsuite/gcc.target/sh/pr54386.c
index ec52d89..b04b212 100644
--- a/gcc/testsuite/gcc.target/sh/pr54386.c
+++ b/gcc/testsuite/gcc.target/sh/pr54386.c
@@ -1,7 +1,6 @@ 
 /* Check that the inlined mem load is not handled as unaligned load.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-not "shll|extu|or" } } */
 
 static inline int
diff --git a/gcc/testsuite/gcc.target/sh/pr54602-1.c b/gcc/testsuite/gcc.target/sh/pr54602-1.c
index bd402b3..e7fb2a9 100644
--- a/gcc/testsuite/gcc.target/sh/pr54602-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr54602-1.c
@@ -3,7 +3,6 @@ 
    expected we won't see any nop insns.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-not "nop" } } */
 
 int test00 (int a, int b);
diff --git a/gcc/testsuite/gcc.target/sh/pr54685.c b/gcc/testsuite/gcc.target/sh/pr54685.c
index 111a120..ed84a32 100644
--- a/gcc/testsuite/gcc.target/sh/pr54685.c
+++ b/gcc/testsuite/gcc.target/sh/pr54685.c
@@ -2,7 +2,6 @@ 
    utilizing the cmp/pz instruction.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-not "not\[ \t\]" } } */
 /* { dg-final { scan-assembler-times "cmp/pz" 7 } } */
 /* { dg-final { scan-assembler-times "shll" 1 } } */
diff --git a/gcc/testsuite/gcc.target/sh/pr54760-1.c b/gcc/testsuite/gcc.target/sh/pr54760-1.c
index 4437511..8bc5836 100644
--- a/gcc/testsuite/gcc.target/sh/pr54760-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr54760-1.c
@@ -2,7 +2,6 @@ 
    built-in functions result in gbr store / load instructions.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "ldc" 1 } } */
 /* { dg-final { scan-assembler-times "stc" 1 } } */
 /* { dg-final { scan-assembler-times "gbr" 2 } } */
diff --git a/gcc/testsuite/gcc.target/sh/pr54760-2.c b/gcc/testsuite/gcc.target/sh/pr54760-2.c
index 4a3561a..bad478c 100644
--- a/gcc/testsuite/gcc.target/sh/pr54760-2.c
+++ b/gcc/testsuite/gcc.target/sh/pr54760-2.c
@@ -3,7 +3,6 @@ 
    instruction something is not working properly.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "stc\tgbr" 0 } } */
 
 /* ---------------------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/sh/pr54760-3.c b/gcc/testsuite/gcc.target/sh/pr54760-3.c
index 678fb39..617a66b 100644
--- a/gcc/testsuite/gcc.target/sh/pr54760-3.c
+++ b/gcc/testsuite/gcc.target/sh/pr54760-3.c
@@ -4,7 +4,6 @@ 
    independent thread_pointer built-in functions available.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 
 int
 test00 (void* p, int x)
diff --git a/gcc/testsuite/gcc.target/sh/pr54760-4.c b/gcc/testsuite/gcc.target/sh/pr54760-4.c
index d218281..bc7cefd 100644
--- a/gcc/testsuite/gcc.target/sh/pr54760-4.c
+++ b/gcc/testsuite/gcc.target/sh/pr54760-4.c
@@ -3,7 +3,6 @@ 
    register, i.e. it is invalidated by function calls.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1 -fcall-used-gbr" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler "stc\tgbr" } } */
 
 extern int test00 (void);
diff --git a/gcc/testsuite/gcc.target/sh/pr54760-5.c b/gcc/testsuite/gcc.target/sh/pr54760-5.c
index 30dfd31..824025d 100644
--- a/gcc/testsuite/gcc.target/sh/pr54760-5.c
+++ b/gcc/testsuite/gcc.target/sh/pr54760-5.c
@@ -3,7 +3,6 @@ 
    call saved register.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1 -fcall-saved-gbr" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-not "stc\tgbr" } } */
 
 typedef struct
diff --git a/gcc/testsuite/gcc.target/sh/pr54760-6.c b/gcc/testsuite/gcc.target/sh/pr54760-6.c
index 4bf94c3..59f0d75 100644
--- a/gcc/testsuite/gcc.target/sh/pr54760-6.c
+++ b/gcc/testsuite/gcc.target/sh/pr54760-6.c
@@ -3,7 +3,6 @@ 
    are.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-not "stc\tgbr" } } */
 
 typedef struct
diff --git a/gcc/testsuite/gcc.target/sh/pr55146.c b/gcc/testsuite/gcc.target/sh/pr55146.c
index 91f0935..ef6ecd1 100644
--- a/gcc/testsuite/gcc.target/sh/pr55146.c
+++ b/gcc/testsuite/gcc.target/sh/pr55146.c
@@ -1,7 +1,6 @@ 
 /* Check that the 'extu.b' instruction is generated for short jump tables.  */
 /* { dg-do compile }  */
 /* { dg-options "-Os" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler "extu.b" } } */
 
 int
diff --git a/gcc/testsuite/gcc.target/sh/pr55160.c b/gcc/testsuite/gcc.target/sh/pr55160.c
index dca15c9..996c4ca 100644
--- a/gcc/testsuite/gcc.target/sh/pr55160.c
+++ b/gcc/testsuite/gcc.target/sh/pr55160.c
@@ -1,7 +1,6 @@ 
 /* Check that the decrement-and-test instruction is generated.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-times "dt\tr" 2 } } */
 
 int
diff --git a/gcc/testsuite/gcc.target/sh/pr59278.c b/gcc/testsuite/gcc.target/sh/pr59278.c
index 563e5b7..2040ffa 100644
--- a/gcc/testsuite/gcc.target/sh/pr59278.c
+++ b/gcc/testsuite/gcc.target/sh/pr59278.c
@@ -1,7 +1,6 @@ 
 /* Check that combine considers unused regs dead.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler "addc" } }  */
 
 struct result
diff --git a/gcc/testsuite/gcc.target/sh/pr59401-1.c b/gcc/testsuite/gcc.target/sh/pr59401-1.c
index a2afe1a..408a270 100644
--- a/gcc/testsuite/gcc.target/sh/pr59401-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr59401-1.c
@@ -3,7 +3,6 @@ 
    and a GBR memory access must not be done.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler "stc\tgbr" } } */
 /* { dg-final { scan-assembler "bf|bt" } } */
 
diff --git a/gcc/testsuite/gcc.target/sh/pr59533-1.c b/gcc/testsuite/gcc.target/sh/pr59533-1.c
index c5c6c7e..b046985 100644
--- a/gcc/testsuite/gcc.target/sh/pr59533-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr59533-1.c
@@ -1,7 +1,6 @@ 
 /* Check that the cmp/pz instruction is generated as expected.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 
 /* { dg-final { scan-assembler-times "shll" 1 } }  */
 /* { dg-final { scan-assembler-times "movt" 5 } }  */
diff --git a/gcc/testsuite/gcc.target/sh/pr63260.c b/gcc/testsuite/gcc.target/sh/pr63260.c
index d01885f..ceff756 100644
--- a/gcc/testsuite/gcc.target/sh/pr63260.c
+++ b/gcc/testsuite/gcc.target/sh/pr63260.c
@@ -2,7 +2,6 @@ 
    fabs instructions.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-final { scan-assembler-not "fpscr|fpchg" } } */
 
 float
diff --git a/gcc/testsuite/gcc.target/sh/pragma-isr-trap-exit.c b/gcc/testsuite/gcc.target/sh/pragma-isr-trap-exit.c
index 6dbd8e7..2a6728f 100644
--- a/gcc/testsuite/gcc.target/sh/pragma-isr-trap-exit.c
+++ b/gcc/testsuite/gcc.target/sh/pragma-isr-trap-exit.c
@@ -1,6 +1,5 @@ 
 /* Check whether trapa is generated only for an ISR.  */
 /* { dg-do compile }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-options "-O" }  */
 /* { dg-final { scan-assembler-times "trapa\[ \t\]\[ \t\]*#4" 1 } }  */
 
diff --git a/gcc/testsuite/gcc.target/sh/pragma-isr-trapa.c b/gcc/testsuite/gcc.target/sh/pragma-isr-trapa.c
index b70be6e..d2a9e60 100644
--- a/gcc/testsuite/gcc.target/sh/pragma-isr-trapa.c
+++ b/gcc/testsuite/gcc.target/sh/pragma-isr-trapa.c
@@ -1,6 +1,5 @@ 
 /* Check that no interrupt-specific register saves are generated.  */
 /* { dg-do compile { target { { "sh*-*-*" } && nonpic } } }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-options "-O" }  */
 /* { dg-final { scan-assembler-times "rte" 1 } }  */
 /* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } }  */
diff --git a/gcc/testsuite/gcc.target/sh/strlen.c b/gcc/testsuite/gcc.target/sh/strlen.c
index 7f2d519..ca88026 100644
--- a/gcc/testsuite/gcc.target/sh/strlen.c
+++ b/gcc/testsuite/gcc.target/sh/strlen.c
@@ -2,7 +2,6 @@ 
    when optimizing for speed.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
 /* { dg-final { scan-assembler-not "jmp" } } */
 /* { dg-final { scan-assembler-times "cmp/str" 2 } } */
 /* { dg-final { scan-assembler-times "tst\t#3" 1 } } */
diff --git a/gcc/testsuite/gcc.target/sh/torture/pr30807.c b/gcc/testsuite/gcc.target/sh/torture/pr30807.c
index c9cc771..256d419 100644
--- a/gcc/testsuite/gcc.target/sh/torture/pr30807.c
+++ b/gcc/testsuite/gcc.target/sh/torture/pr30807.c
@@ -1,6 +1,5 @@ 
 /* { dg-do compile }  */
 /* { dg-additional-options "-fpic -std=c99" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 
 typedef unsigned int size_t;
 typedef struct
diff --git a/gcc/testsuite/gcc.target/sh/torture/pr34777.c b/gcc/testsuite/gcc.target/sh/torture/pr34777.c
index de6ba02..052709e 100644
--- a/gcc/testsuite/gcc.target/sh/torture/pr34777.c
+++ b/gcc/testsuite/gcc.target/sh/torture/pr34777.c
@@ -1,6 +1,5 @@ 
 /* { dg-do compile }  */
 /* { dg-additional-options "-fschedule-insns -fPIC -mprefergot" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 
 static __inline __attribute__ ((__always_inline__)) void *
 _dl_mmap (void * start, int length, int prot, int flags, int fd,
diff --git a/gcc/testsuite/gcc.target/sh/torture/pr64652.c b/gcc/testsuite/gcc.target/sh/torture/pr64652.c
index 8144311..eeb1c42 100644
--- a/gcc/testsuite/gcc.target/sh/torture/pr64652.c
+++ b/gcc/testsuite/gcc.target/sh/torture/pr64652.c
@@ -1,7 +1,6 @@ 
 /* Check that using -mdiv=call-fp compiles without fuzz.  */
 /* { dg-do compile }  */
 /* { dg-additional-options "-mdiv=call-fp" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 
 int
 test_0 (int a, int b, int c, int d)
diff --git a/gcc/testsuite/gcc.target/sh/torture/pr65505.c b/gcc/testsuite/gcc.target/sh/torture/pr65505.c
index 3e93002..934092c 100644
--- a/gcc/testsuite/gcc.target/sh/torture/pr65505.c
+++ b/gcc/testsuite/gcc.target/sh/torture/pr65505.c
@@ -1,6 +1,5 @@ 
 /* { dg-do compile }  */
 /* { dg-additional-options "-std=gnu99" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 
 struct thread_info {
  struct task_struct *task;
diff --git a/gcc/testsuite/gcc.target/sh/torture/pragma-isr.c b/gcc/testsuite/gcc.target/sh/torture/pragma-isr.c
index 9e665ba..66e71f4 100644
--- a/gcc/testsuite/gcc.target/sh/torture/pragma-isr.c
+++ b/gcc/testsuite/gcc.target/sh/torture/pragma-isr.c
@@ -1,6 +1,5 @@ 
 /* Check whether rte is generated for two ISRs.  */
 /* { dg-do compile }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "rte" 2 } }  */
 
 extern void foo (void);
diff --git a/gcc/testsuite/gcc.target/sh/torture/pragma-isr2.c b/gcc/testsuite/gcc.target/sh/torture/pragma-isr2.c
index ce984e7..e7f5129 100644
--- a/gcc/testsuite/gcc.target/sh/torture/pragma-isr2.c
+++ b/gcc/testsuite/gcc.target/sh/torture/pragma-isr2.c
@@ -1,6 +1,5 @@ 
 /* Check whether rte is generated only for an ISRs.  */
 /* { dg-do compile }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "rte" 1 } }  */
 
 #pragma interrupt