From patchwork Mon Feb 29 08:46:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 589778 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 080EB1402D2 for ; Mon, 29 Feb 2016 19:48:23 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=tCxrQcOi; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=o2eOZefAM7mD/OGNDI2hVSSop0sqJ3LOy7TvxPJQatdXIUC/MUKPK lx+1T4C63S5rKLi2KHBNHbMKKOwjdNqilP1HiAHAlQr5eog+6S6Pm6hQL6jPhuEQ YTRsGZvLH6M45Hodt9I+SpZV5KKdtX4+wxrz/zW7/2FvESazEB6ngw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=CDUolxahC5C55GOW7nugmFNHPxQ=; b=tCxrQcOiHrFKx4nKI1uN KQUgqCQBJsXzGciBcULw3Vxd1CFV+eKUouaJKj64wReIMRKzQ1pf9GnXj65qb14l FfyrL3lwM3/qLne6Dqzh/NmMkRdZC+xXY+L1WjVDPBdVvMaBgKByNtU1O5rH2ARQ tQk+MDFvevnUJjUHmkRJfSY= Received: (qmail 76322 invoked by alias); 29 Feb 2016 08:46:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 76260 invoked by uid 89); 29 Feb 2016 08:46:54 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.2 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=t4, 8-bit, tdi, dbl X-HELO: e06smtp14.uk.ibm.com Received: from e06smtp14.uk.ibm.com (HELO e06smtp14.uk.ibm.com) (195.75.94.110) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Mon, 29 Feb 2016 08:46:49 +0000 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Date: Mon, 29 Feb 2016 09:46:38 +0100 Message-Id: <1456735599-21355-9-git-send-email-krebbel@linux.vnet.ibm.com> In-Reply-To: <1456735599-21355-1-git-send-email-krebbel@linux.vnet.ibm.com> References: <1456735599-21355-1-git-send-email-krebbel@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16022908-0017-0000-0000-00000759E2D1 X-IsSubscribed: yes While trying to get rid of the Y constraint in the setmem patterns I noticed that for these patterns it isn't even a problem since these always only use the constraint with a Pmode match_operand. But while being at it I've tried to fold some of the patterns a bit. gcc/ChangeLog: 2016-02-29 Andreas Krebbel * config/s390/constraints.md ("jm8"): New constraint. * config/s390/predicates.md ("const_int_8bitset_operand"): New predicate. * config/s390/s390.md ("*setmem_long", "*setmem_long_and"): Merge into ... ("*setmem_long"): New pattern. ("*setmem_long_31z", "*setmem_long_and_31z"): Merge into ... ("*setmem_long_31z"): New pattern. * config/s390/subst.md ("setmem_31z_subst", "setmem_and_subst"): New substitution rules with the required attributes. --- gcc/config/s390/constraints.md | 5 +++++ gcc/config/s390/predicates.md | 6 ++++++ gcc/config/s390/s390.md | 35 ++--------------------------------- gcc/config/s390/subst.md | 25 +++++++++++++++++++++++++ 4 files changed, 38 insertions(+), 33 deletions(-) diff --git a/gcc/config/s390/constraints.md b/gcc/config/s390/constraints.md index 60a7edf..6eeaa98 100644 --- a/gcc/config/s390/constraints.md +++ b/gcc/config/s390/constraints.md @@ -37,6 +37,7 @@ ;; jKK: constant vector with all elements having the same value and ;; matching K constraint ;; jm6: An integer operand with the lowest order 6 bits all ones. +;; jm8: An integer operand with the lowest order 8 bits all ones. ;; t -- Access registers 36 and 37. ;; v -- Vector registers v0-v31. ;; C -- A signed 8-bit constant (-128..127) @@ -420,6 +421,10 @@ "@internal An integer operand with the lowest order 6 bits all ones." (match_operand 0 "const_int_6bitset_operand")) +(define_constraint "jm8" + "@internal An integer operand with the lowest order 8 bits all ones." + (match_operand 0 "const_int_8bitset_operand")) + ;; ;; Memory constraints follow. ;; diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md index fefefb3..fbff24d 100644 --- a/gcc/config/s390/predicates.md +++ b/gcc/config/s390/predicates.md @@ -119,6 +119,12 @@ (define_predicate "const_int_6bitset_operand" (and (match_code "const_int") (match_test "(INTVAL (op) & 63) == 63"))) + +; An integer operand with the lowest order 8 bits all ones. +(define_predicate "const_int_8bitset_operand" + (and (match_code "const_int") + (match_test "(INTVAL (op) & 255) == 255"))) + (define_predicate "nonzero_shift_count_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)"))) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index ca58c42..d085fa1 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -3323,7 +3323,7 @@ ; Patterns for 31 bit + Esa and 64 bit + Zarch. -(define_insn "*setmem_long" +(define_insn "*setmem_long" [(clobber (match_operand: 0 "register_operand" "=d")) (set (mem:BLK (subreg:P (match_operand: 3 "register_operand" "0") 0)) (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "Y") @@ -3336,26 +3336,10 @@ [(set_attr "length" "8") (set_attr "type" "vs")]) -(define_insn "*setmem_long_and" - [(clobber (match_operand: 0 "register_operand" "=d")) - (set (mem:BLK (subreg:P (match_operand: 3 "register_operand" "0") 0)) - (unspec:BLK [(and:P - (match_operand:P 2 "shift_count_or_setmem_operand" "Y") - (match_operand:P 4 "const_int_operand" "n")) - (subreg:P (match_dup 3) )] - UNSPEC_REPLICATE_BYTE)) - (use (match_operand: 1 "register_operand" "d")) - (clobber (reg:CC CC_REGNUM))] - "(TARGET_64BIT || !TARGET_ZARCH) && - (INTVAL (operands[4]) & 255) == 255" - "mvcle\t%0,%1,%Y2\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets ; of the SImode subregs. -(define_insn "*setmem_long_31z" +(define_insn "*setmem_long_31z" [(clobber (match_operand:TI 0 "register_operand" "=d")) (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "Y") @@ -3367,21 +3351,6 @@ [(set_attr "length" "8") (set_attr "type" "vs")]) -(define_insn "*setmem_long_and_31z" - [(clobber (match_operand:TI 0 "register_operand" "=d")) - (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) - (unspec:BLK [(and:SI - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 4 "const_int_operand" "n")) - (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) - (use (match_operand:TI 1 "register_operand" "d")) - (clobber (reg:CC CC_REGNUM))] - "(!TARGET_64BIT && TARGET_ZARCH) && - (INTVAL (operands[4]) & 255) == 255" - "mvcle\t%0,%1,%Y2\;jo\t.-4" - [(set_attr "length" "8") - (set_attr "type" "vs")]) - ; ; cmpmemM instruction pattern(s). ; diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md index 8a1b814..886d420 100644 --- a/gcc/config/s390/subst.md +++ b/gcc/config/s390/subst.md @@ -120,3 +120,28 @@ (clobber (match_scratch:DSI 0 "=d,d"))]) (define_subst_attr "cconly" "cconly_subst" "" "_cconly") + + +;; setmem substitution patterns + +; Add an AND operation on the padding byte operand. Only the lowest 8 +; bit are used and the rest is ignored. +(define_subst "setmem_and_subst" + [(clobber (match_operand:TDI 0 "register_operand" "")) + (set (mem:BLK (subreg:DSI (match_operand:TDI 1 "register_operand" "") 0)) + (unspec:BLK [(match_operand:DSI 2 "shift_count_or_setmem_operand" "") + (match_operand:DSI 3 "register_operand" "")] + UNSPEC_REPLICATE_BYTE)) + (use (match_operand:TDI 4 "register_operand" "")) + (clobber (reg:CC CC_REGNUM))] +"" + [(clobber (match_dup 0)) + (set (mem:BLK (subreg:DSI (match_dup 1) 0)) + (unspec:BLK [(and:DSI (match_dup 2) + (match_operand:DSI 5 "const_int_8bitset_operand" "jm8")) + (match_dup 3)] + UNSPEC_REPLICATE_BYTE)) + (use (match_dup 4)) + (clobber (reg:CC CC_REGNUM))]) + +(define_subst_attr "setmem_and" "setmem_and_subst" "" "_and")