From patchwork Mon Feb 29 08:46:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 589782 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id EEEC11402D2 for ; Mon, 29 Feb 2016 19:49:07 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=MHyzDf4r; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=RE1SPYuMPFFnBn55KqNFvdw9mEhV2LIQ5qPRWH66JScR4qG5VQaYg ll+K17Y10m1lI4QOYE04oIfOwgRwqqYD5LqXOMXGitkR4fYQWzP9O2bo8BIaeIp1 B4SJ1/IoU15MblrlYq29gWgpQa5EBmfwLvtIHIs4i8b1pnYrFurXp8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=svhmLMlfgm07y82P02d1KQiBWyw=; b=MHyzDf4ry0O8gd+0cbhl sqGCYQFR/dGfmpFS11SeoY9+eEnT9tky+DHQuDBe7XVKKskpP9Olv7KHuU4bKWsr lGX4az1r8TP7UXmhtXRWGcyMMjnA0mEg+XIQSgXAU40/TYFbBRCbjp4+citNofmr /giFRiNIrlAqQRNuPnC/06k= Received: (qmail 77341 invoked by alias); 29 Feb 2016 08:47:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 77283 invoked by uid 89); 29 Feb 2016 08:47:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=3.3 required=5.0 tests=AWL, BAYES_20, KAM_LAZY_DOMAIN_SECURITY, MEDICAL_SUBJECT, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=ii, vector.md, UD:vector.md, vectormd X-HELO: e06smtp15.uk.ibm.com Received: from e06smtp15.uk.ibm.com (HELO e06smtp15.uk.ibm.com) (195.75.94.111) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Mon, 29 Feb 2016 08:46:50 +0000 Received: from localhost by e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Date: Mon, 29 Feb 2016 09:46:37 +0100 Message-Id: <1456735599-21355-8-git-send-email-krebbel@linux.vnet.ibm.com> In-Reply-To: <1456735599-21355-1-git-send-email-krebbel@linux.vnet.ibm.com> References: <1456735599-21355-1-git-send-email-krebbel@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16022908-0021-0000-0000-000020558E9A X-IsSubscribed: yes This finally removes the Y constraint from the vector patterns while folding some of them using a code iterator. gcc/ChangeLog: 2016-02-29 Andreas Krebbel * config/s390/subst.md (DSI_VI): New mode iterator. ("addr_style_op_subst"): Use DSI_VI instead of DSI. * config/s390/vector.md ("vec_set"): Move expander before the insn definition. ("*vec_set"): Change predicate and add alternative to support only either register or const_int operands as element selector. ("*vec_set_plus"): New pattern to support reg + const_int operands. ("vec_extract"): New expander. ("*vec_extract"): New insn definition supporting reg and const_int element selectors. ("*vec_extract_plus"): New insn definition supporting reg+const_int element selectors. ("rotl3", "ashl3", "ashr3"): Merge into the following expander+insn definition. ("3"): New expander. ("*3"): New insn definition. --- gcc/config/s390/subst.md | 13 ++--- gcc/config/s390/vector.md | 127 +++++++++++++++++++++++++++------------------- 2 files changed, 81 insertions(+), 59 deletions(-) diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md index 3becf20..8a1b814 100644 --- a/gcc/config/s390/subst.md +++ b/gcc/config/s390/subst.md @@ -20,19 +20,20 @@ ;; . (define_code_iterator SUBST [rotate ashift lshiftrt ashiftrt]) +(define_mode_iterator DSI_VI [SI DI V2QI V4QI V8QI V16QI V2HI V4HI V8HI V2SI V4SI V2DI]) ; This expands an register/immediate operand to a register+immediate ; operand to draw advantage of the address style operand format ; providing a addition for free. (define_subst "addr_style_op_subst" - [(set (match_operand:DSI 0 "" "") - (SUBST:DSI (match_operand:DSI 1 "" "") - (match_operand:SI 2 "" "")))] + [(set (match_operand:DSI_VI 0 "" "") + (SUBST:DSI_VI (match_operand:DSI_VI 1 "" "") + (match_operand:SI 2 "" "")))] "" [(set (match_dup 0) - (SUBST:DSI (match_dup 1) - (plus:SI (match_operand:SI 2 "register_operand" "a") - (match_operand 3 "const_int_operand" "n"))))]) + (SUBST:DSI_VI (match_dup 1) + (plus:SI (match_operand:SI 2 "register_operand" "a") + (match_operand 3 "const_int_operand" "n"))))]) ; Use this in the insn name. (define_subst_attr "addr_style_op" "addr_style_op_subst" "" "_plus") diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index cc3287c..2b8e9bf 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -307,47 +307,82 @@ ; vec_store_lanes? +; vec_set is supposed to *modify* an existing vector so operand 0 is +; duplicated as input operand. +(define_expand "vec_set" + [(set (match_operand:V 0 "register_operand" "") + (unspec:V [(match_operand: 1 "general_operand" "") + (match_operand:SI 2 "shift_count_or_setmem_operand" "") + (match_dup 0)] + UNSPEC_VEC_SET))] + "TARGET_VX") + ; FIXME: Support also vector mode operands for 1 ; FIXME: A target memory operand seems to be useful otherwise we end ; up with vl vlvgg vst. Shouldn't the middle-end be able to handle ; that itself? (define_insn "*vec_set" - [(set (match_operand:V 0 "register_operand" "=v, v,v") - (unspec:V [(match_operand: 1 "general_operand" "d,QR,K") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y, I,I") - (match_operand:V 3 "register_operand" "0, 0,0")] + [(set (match_operand:V 0 "register_operand" "=v, v,v") + (unspec:V [(match_operand: 1 "general_operand" "d,QR,K") + (match_operand:SI 2 "nonmemory_operand" "an, I,I") + (match_operand:V 3 "register_operand" "0, 0,0")] UNSPEC_VEC_SET))] - "TARGET_VX" + "TARGET_VX + && (!CONST_INT_P (operands[2]) + || UINTVAL (operands[2]) < GET_MODE_NUNITS (mode))" "@ vlvg\t%v0,%1,%Y2 vle\t%v0,%1,%2 vlei\t%v0,%1,%2" [(set_attr "op_type" "VRS,VRX,VRI")]) -; vec_set is supposed to *modify* an existing vector so operand 0 is -; duplicated as input operand. -(define_expand "vec_set" - [(set (match_operand:V 0 "register_operand" "") - (unspec:V [(match_operand: 1 "general_operand" "") - (match_operand:SI 2 "shift_count_or_setmem_operand" "") - (match_dup 0)] - UNSPEC_VEC_SET))] - "TARGET_VX") +(define_insn "*vec_set_plus" + [(set (match_operand:V 0 "register_operand" "=v") + (unspec:V [(match_operand: 1 "general_operand" "d") + (plus:SI (match_operand:SI 2 "register_operand" "a") + (match_operand:SI 4 "const_int_operand" "n")) + (match_operand:V 3 "register_operand" "0")] + UNSPEC_VEC_SET))] + "TARGET_VX" + "vlvg\t%v0,%1,%4(%2)" + [(set_attr "op_type" "VRS")]) + ; FIXME: Support also vector mode operands for 0 ; FIXME: This should be (vec_select ..) or something but it does only allow constant selectors :( ; This is used via RTL standard name as well as for expanding the builtin -(define_insn "vec_extract" - [(set (match_operand: 0 "nonimmediate_operand" "=d,QR") - (unspec: [(match_operand:V 1 "register_operand" " v, v") - (match_operand:SI 2 "shift_count_or_setmem_operand" " Y, I")] +(define_expand "vec_extract" + [(set (match_operand: 0 "nonimmediate_operand" "") + (unspec: [(match_operand:V 1 "register_operand" "") + (match_operand:SI 2 "shift_count_or_setmem_operand" "")] UNSPEC_VEC_EXTRACT))] - "TARGET_VX" + "TARGET_VX") + +(define_insn "*vec_extract" + [(set (match_operand: 0 "nonimmediate_operand" "=d,QR") + (unspec: [(match_operand:V 1 "register_operand" "v, v") + (match_operand:SI 2 "nonmemory_operand" "an, I")] + UNSPEC_VEC_EXTRACT))] + "TARGET_VX + && (!CONST_INT_P (operands[2]) + || UINTVAL (operands[2]) < GET_MODE_NUNITS (mode))" "@ vlgv\t%0,%v1,%Y2 vste\t%v1,%0,%2" [(set_attr "op_type" "VRS,VRX")]) +(define_insn "*vec_extract_plus" + [(set (match_operand: 0 "nonimmediate_operand" "=d,QR") + (unspec: [(match_operand:V 1 "register_operand" "v, v") + (plus:SI (match_operand:SI 2 "nonmemory_operand" "a, I") + (match_operand:SI 3 "const_int_operand" "n, I"))] + UNSPEC_VEC_EXTRACT))] + "TARGET_VX" + "@ + vlgv\t%0,%v1,%3(%2) + vste\t%v1,%0,%2" + [(set_attr "op_type" "VRS,VRX")]) + (define_expand "vec_init" [(match_operand:V_HW 0 "register_operand" "") (match_operand:V_HW 1 "nonmemory_operand" "")] @@ -667,17 +702,6 @@ [(set_attr "op_type" "VRR")]) -; Vector rotate instructions - -; Each vector element rotated by a scalar -; verllb, verllh, verllf, verllg -(define_insn "rotl3" - [(set (match_operand:VI 0 "register_operand" "=v") - (rotate:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] - "TARGET_VX" - "verll\t%v0,%v1,%Y2" - [(set_attr "op_type" "VRS")]) ; Each vector element rotated by the corresponding vector element ; verllvb, verllvh, verllvf, verllvg @@ -690,36 +714,33 @@ [(set_attr "op_type" "VRR")]) -; Shift each element by scalar value +; Vector rotate and shift by scalar instructions -; veslb, veslh, veslf, veslg -(define_insn "ashl3" - [(set (match_operand:VI 0 "register_operand" "=v") - (ashift:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] - "TARGET_VX" - "vesl\t%v0,%v1,%Y2" - [(set_attr "op_type" "VRS")]) +(define_code_iterator VEC_SHIFTS [ashift ashiftrt lshiftrt rotate]) +(define_code_attr vec_shifts_name [(ashift "ashl") (ashiftrt "ashr") + (lshiftrt "lshr") (rotate "rotl")]) +(define_code_attr vec_shifts_mnem [(ashift "vesl") (ashiftrt "vesra") + (lshiftrt "vesrl") (rotate "verll")]) -; vesrab, vesrah, vesraf, vesrag -(define_insn "ashr3" - [(set (match_operand:VI 0 "register_operand" "=v") - (ashiftrt:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] - "TARGET_VX" - "vesra\t%v0,%v1,%Y2" - [(set_attr "op_type" "VRS")]) +; Each vector element rotated by a scalar +(define_expand "3" + [(set (match_operand:VI 0 "register_operand" "") + (VEC_SHIFTS:VI (match_operand:VI 1 "register_operand" "") + (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] + "TARGET_VX") +; verllb, verllh, verllf, verllg +; veslb, veslh, veslf, veslg +; vesrab, vesrah, vesraf, vesrag ; vesrlb, vesrlh, vesrlf, vesrlg -(define_insn "lshr3" - [(set (match_operand:VI 0 "register_operand" "=v") - (lshiftrt:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] +(define_insn "*3" + [(set (match_operand:VI 0 "register_operand" "=v") + (VEC_SHIFTS:VI (match_operand:VI 1 "register_operand" "v") + (match_operand:SI 2 "nonmemory_operand" "an")))] "TARGET_VX" - "vesrl\t%v0,%v1,%Y2" + "\t%v0,%v1,%Y2" [(set_attr "op_type" "VRS")]) - ; Shift each element by corresponding vector element ; veslvb, veslvh, veslvf, veslvg