From patchwork Mon Feb 29 08:46:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 589775 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5C1F5140324 for ; Mon, 29 Feb 2016 19:47:37 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=it4Auh+d; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=xshIOAB81GXlwIeoNNFkWUAXF1k6TjC8DSXPEmrxUMTTxD4NnETgf bEC9HCGPkMGZzdp+RD8CRW1IeGm20xuOZIa5jt/9Ye1teDlpb40nEGEuRaK/LX9d ea/zMUaQ4AQomncGUKVCWb6Hjuo4LzprB0RBXncMjSIFgx8RIkFg+U= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=pVv3jwnP+z8Jfb41g2gxBogcX8k=; b=it4Auh+dE/jvn0QT6rrC R2mkSe8MJIHZ4Dx2ysdHI3jIDnyg1X73fbhkaJEJJWbalEMIgzSCMOLepGvBl0RP f0zEjuya+mrGNYGO+6tm4gAb+wKr8ZK/HXJYbZskWdWtCrI0zxYSF1yg2EvP1niZ a1/pN/bVHRrAJD77LlNCQJM= Received: (qmail 75665 invoked by alias); 29 Feb 2016 08:46:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 75449 invoked by uid 89); 29 Feb 2016 08:46:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.1 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=nn, srl, yy, 19, 7 X-HELO: e06smtp14.uk.ibm.com Received: from e06smtp14.uk.ibm.com (HELO e06smtp14.uk.ibm.com) (195.75.94.110) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Mon, 29 Feb 2016 08:46:46 +0000 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Date: Mon, 29 Feb 2016 09:46:34 +0100 Message-Id: <1456735599-21355-5-git-send-email-krebbel@linux.vnet.ibm.com> In-Reply-To: <1456735599-21355-1-git-send-email-krebbel@linux.vnet.ibm.com> References: <1456735599-21355-1-git-send-email-krebbel@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16022908-0017-0000-0000-00000759E2CA X-IsSubscribed: yes With this patch the substitution patterns added earlier are used for the logical right shift and all the left shift patterns. 2016-02-29 Andreas Krebbel * config/s390/s390.md ("3"): Change predicate of op2 to nonmemory_operand. ("*di3_31", "*di3_31_and"): Merge into single pattern definition ... ("*di3_31"): New pattern. ("*3", "*3_and"): Merge into single pattern definition ... ("*3"): New pattern. * config/s390/subst.md: Add ashift and lshiftrt to SUBST iterator. --- gcc/config/s390/s390.md | 55 ++++++++++++++---------------------------------- gcc/config/s390/subst.md | 2 +- 2 files changed, 17 insertions(+), 40 deletions(-) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index b7c037a..771d1e9 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -8408,60 +8408,37 @@ (define_expand "3" [(set (match_operand:DSI 0 "register_operand" "") (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") - (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] + (match_operand:SI 2 "nonmemory_operand" "")))] "" "") +; ESA 64 bit register pair shift with reg or imm shift count ; sldl, srdl -(define_insn "*di3_31" - [(set (match_operand:DI 0 "register_operand" "=d") - (SHIFT:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] +(define_insn "*di3_31" + [(set (match_operand:DI 0 "register_operand" "=d") + (SHIFT:DI (match_operand:DI 1 "register_operand" "0") + (match_operand:SI 2 "nonmemory_operand" "an")))] "!TARGET_ZARCH" - "sdl\t%0,%Y2" + "sdl\t%0," [(set_attr "op_type" "RS") (set_attr "atype" "reg") (set_attr "z196prop" "z196_cracked")]) -; sll, srl, sllg, srlg, sllk, srlk -(define_insn "*3" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (SHIFT:GPR (match_operand:GPR 1 "register_operand" ",d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] - "" - "@ - sl\t%0,<1>%Y2 - sl\t%0,%1,%Y2" - [(set_attr "op_type" "RS,RSY") - (set_attr "atype" "reg,reg") - (set_attr "cpu_facility" "*,z196") - (set_attr "z10prop" "z10_super_E1,*")]) - -; sldl, srdl -(define_insn "*di3_31_and" - [(set (match_operand:DI 0 "register_operand" "=d") - (SHIFT:DI (match_operand:DI 1 "register_operand" "0") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))))] - "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" - "sdl\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) +; 64 bit register shift with reg or imm shift count ; sll, srl, sllg, srlg, sllk, srlk -(define_insn "*3_and" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (SHIFT:GPR (match_operand:GPR 1 "register_operand" ",d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") - (match_operand:SI 3 "const_int_operand" "n,n"))))] - "(INTVAL (operands[3]) & 63) == 63" +(define_insn "*3" + [(set (match_operand:GPR 0 "register_operand" "=d, d") + (SHIFT:GPR (match_operand:GPR 1 "register_operand" ", d") + (match_operand:SI 2 "nonmemory_operand" "an,an")))] + "" "@ - sl\t%0,<1>%Y2 - sl\t%0,%1,%Y2" + sl\t%0,<1> + sl\t%0,%1," [(set_attr "op_type" "RS,RSY") (set_attr "atype" "reg,reg") (set_attr "cpu_facility" "*,z196") - (set_attr "z10prop" "z10_super_E1,*")]) + (set_attr "z10prop" "z10_super_E1,*")]) ; ; ashr(di|si)3 instruction pattern(s). diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md index c3761a9..907676a 100644 --- a/gcc/config/s390/subst.md +++ b/gcc/config/s390/subst.md @@ -19,7 +19,7 @@ ;; along with GCC; see the file COPYING3. If not see ;; . -(define_code_iterator SUBST [rotate]) +(define_code_iterator SUBST [rotate ashift lshiftrt]) ; This expands an register/immediate operand to a register+immediate ; operand to draw advantage of the address style operand format