From patchwork Tue Feb 23 14:33:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 586881 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9108E140779 for ; Wed, 24 Feb 2016 01:34:21 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=lF9/8mS4; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=xFD+TRrQm5OYaMWK6f2qRtWFWc2ILzcGJdp+4LudIPRtoDRQWuvy7 TJ0qDl72FB7hcdhCGLWw/qg0ZFmuvkasJQxyd9FkdjCEerLKxyc6x5vMM4P6fj83 7RO1Ju9lFmqCYKVCZu8xqQc6PnT3YMBmRcBaHUEmnO43ugE6tkNyc0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; s=default; bh=CK4sEHfkUVKywejVsTTZpfDSlLg=; b=lF9/8mS4ugwDm82zyFzzFKIQZqzO zF1r4DwgqXQysjPkK/aLDdiLcPQ/FJ6tUEMd4EBUJrMrccbC10Zg0Ch52ph9WDq4 0+n1K6XsSuaEsX4wox/FZsi69ecUHDRHIR4UlSLDipKvxUYzeZF1ubaEGD17LdcC HYLa8VeTxdzlYNs= Received: (qmail 19951 invoked by alias); 23 Feb 2016 14:33:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 19865 invoked by uid 89); 23 Feb 2016 14:33:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.1 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=nn, substitution, 6564, dd X-HELO: e06smtp12.uk.ibm.com Received: from e06smtp12.uk.ibm.com (HELO e06smtp12.uk.ibm.com) (195.75.94.108) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Tue, 23 Feb 2016 14:33:31 +0000 Received: from localhost by e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 23 Feb 2016 14:33:26 -0000 X-IBM-Helo: d06dlp01.portsmouth.uk.ibm.com X-IBM-MailFrom: krebbel@linux.vnet.ibm.com X-IBM-RcptTo: gcc-patches@gcc.gnu.org Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by d06dlp01.portsmouth.uk.ibm.com (Postfix) with ESMTP id B503A17D8042 for ; Tue, 23 Feb 2016 14:33:46 +0000 (GMT) Received: from d06av09.portsmouth.uk.ibm.com (d06av09.portsmouth.uk.ibm.com [9.149.37.250]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u1NEXPCj61669380 for ; Tue, 23 Feb 2016 14:33:25 GMT Received: from d06av09.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av09.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u1NEXPSC023552 for ; Tue, 23 Feb 2016 07:33:25 -0700 Received: from maggie.boeblingen.de.ibm.com (dyn-9-152-212-123.boeblingen.de.ibm.com [9.152.212.123]) by d06av09.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u1NEXOE9023504 (version=TLSv1/SSLv3 cipher=AES256-SHA256 bits=256 verify=NO) for ; Tue, 23 Feb 2016 07:33:25 -0700 From: Andreas Krebbel To: gcc-patches@gcc.gnu.org Subject: [PATCH 5/9] S/390: Get rid of Y constraint in arithmetic right shift patterns. Date: Tue, 23 Feb 2016 15:33:20 +0100 Message-Id: <1456238004-21150-6-git-send-email-krebbel@linux.vnet.ibm.com> In-Reply-To: <1456238004-21150-1-git-send-email-krebbel@linux.vnet.ibm.com> References: <1456238004-21150-1-git-send-email-krebbel@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16022314-0009-0000-0000-000007BCDE92 X-IsSubscribed: yes The arithmetic shift patterns set also the condition code. This adds more substitution potential. Depending on whether the actual result or the CC output will be used 3 different variants of each of these patterns are needed. This multiplied with the PLUS and the AND operands from the earlier substitutions enables a lot of folding. * config/s390/s390.md ("*ashrdi3_cc_31") ("*ashrdi3_cconly_31""*ashrdi3_cc_31_and") ("*ashrdi3_cconly_31_and", "*ashrdi3_31_and", "*ashrdi3_31"): Merge insn definitions into ... ("*ashrdi3_31"): New pattern definition. ("*ashr3_cc", "*ashr3_cconly", "ashr3", ) ("*ashr3_cc_and", "*ashr3_cconly_and") ("*ashr3_and"): Merge insn definitions into ... ("*ashr3"): New pattern definition. * config/s390/subst.md ("addr_style_op_cc_subst") ("masked_op_cc_subst", "setcc_subst", "cconly_subst"): New substitutions patterns plus attributes. --- gcc/config/s390/s390.md | 189 +++++++---------------------------------------- gcc/config/s390/subst.md | 61 +++++++++++++++ 2 files changed, 88 insertions(+), 162 deletions(-) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index b4983cd..a058f58 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -8441,183 +8441,48 @@ [(parallel [(set (match_operand:DSI 0 "register_operand" "") (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") - (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) + (match_operand:SI 2 "nonmemory_operand" ""))) (clobber (reg:CC CC_REGNUM))])] "" "") -(define_insn "*ashrdi3_cc_31" - [(set (reg CC_REGNUM) - (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) - (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d") - (ashiftrt:DI (match_dup 1) (match_dup 2)))] - "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" - "srda\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -(define_insn "*ashrdi3_cconly_31" - [(set (reg CC_REGNUM) - (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) - (const_int 0))) - (clobber (match_scratch:DI 0 "=d"))] - "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" - "srda\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -(define_insn "*ashrdi3_31" - [(set (match_operand:DI 0 "register_operand" "=d") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) +; FIXME: The number of alternatives is doubled here to match the fix +; number of 4 in the subst pattern for the (clobber (match_scratch... +; The right fix should be to support match_scratch in the output +; pattern of a define_subst. +(define_insn "*ashrdi3_31" + [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0,0") + (match_operand:SI 2 "nonmemory_operand" "a,n,a,n"))) (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH" - "srda\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -; sra, srag, srak -(define_insn "*ashr3_cc" - [(set (reg CC_REGNUM) - (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" ",d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) - (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d,d") - (ashiftrt:GPR (match_dup 1) (match_dup 2)))] - "s390_match_ccmode(insn, CCSmode)" "@ - sra\t%0,<1>%Y2 - sra\t%0,%1,%Y2" - [(set_attr "op_type" "RS,RSY") - (set_attr "atype" "reg,reg") - (set_attr "cpu_facility" "*,z196") - (set_attr "z10prop" "z10_super_E1,*")]) + srda\t%0,(%2) + srda\t%0,%Y2 + srda\t%0,(%2) + srda\t%0,%Y2" + [(set_attr "op_type" "RS") + (set_attr "enabled" "*,,*,") + (set_attr "atype" "reg")]) -; sra, srag, srak -(define_insn "*ashr3_cconly" - [(set (reg CC_REGNUM) - (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" ",d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) - (const_int 0))) - (clobber (match_scratch:GPR 0 "=d,d"))] - "s390_match_ccmode(insn, CCSmode)" - "@ - sra\t%0,<1>%Y2 - sra\t%0,%1,%Y2" - [(set_attr "op_type" "RS,RSY") - (set_attr "atype" "reg,reg") - (set_attr "cpu_facility" "*,z196") - (set_attr "z10prop" "z10_super_E1,*")]) ; sra, srag -(define_insn "*ashr3" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (ashiftrt:GPR (match_operand:GPR 1 "register_operand" ",d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))) +(define_insn "*ashr3" + [(set (match_operand:GPR 0 "register_operand" "=d, d,d,d") + (ashiftrt:GPR (match_operand:GPR 1 "register_operand" ",,d,d") + (match_operand:SI 2 "nonmemory_operand" "a, n,a,n"))) (clobber (reg:CC CC_REGNUM))] "" "@ + sra\t%0,<1>(%2) sra\t%0,<1>%Y2 + sra\t%0,%1,(%2) sra\t%0,%1,%Y2" - [(set_attr "op_type" "RS,RSY") - (set_attr "atype" "reg,reg") - (set_attr "cpu_facility" "*,z196") - (set_attr "z10prop" "z10_super_E1,*")]) - - -; shift pattern with implicit ANDs - -(define_insn "*ashrdi3_cc_31_and" - [(set (reg CC_REGNUM) - (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))) - (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=d") - (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] - "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) - && (INTVAL (operands[3]) & 63) == 63" - "srda\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -(define_insn "*ashrdi3_cconly_31_and" - [(set (reg CC_REGNUM) - (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))) - (const_int 0))) - (clobber (match_scratch:DI 0 "=d"))] - "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) - && (INTVAL (operands[3]) & 63) == 63" - "srda\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -(define_insn "*ashrdi3_31_and" - [(set (match_operand:DI 0 "register_operand" "=d") - (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n")))) - (clobber (reg:CC CC_REGNUM))] - "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" - "srda\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -; sra, srag, srak -(define_insn "*ashr3_cc_and" - [(set (reg CC_REGNUM) - (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" ",d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") - (match_operand:SI 3 "const_int_operand" "n,n"))) - (const_int 0))) - (set (match_operand:GPR 0 "register_operand" "=d,d") - (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] - "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" - "@ - sra\t%0,<1>%Y2 - sra\t%0,%1,%Y2" - [(set_attr "op_type" "RS,RSY") - (set_attr "atype" "reg,reg") - (set_attr "cpu_facility" "*,z196") - (set_attr "z10prop" "z10_super_E1,*")]) - -; sra, srag, srak -(define_insn "*ashr3_cconly_and" - [(set (reg CC_REGNUM) - (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" ",d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") - (match_operand:SI 3 "const_int_operand" "n,n"))) - (const_int 0))) - (clobber (match_scratch:GPR 0 "=d,d"))] - "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" - "@ - sra\t%0,<1>%Y2 - sra\t%0,%1,%Y2" - [(set_attr "op_type" "RS,RSY") - (set_attr "atype" "reg,reg") - (set_attr "cpu_facility" "*,z196") - (set_attr "z10prop" "z10_super_E1,*")]) - -; sra, srag, srak -(define_insn "*ashr3_and" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (ashiftrt:GPR (match_operand:GPR 1 "register_operand" ",d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") - (match_operand:SI 3 "const_int_operand" "n,n")))) - (clobber (reg:CC CC_REGNUM))] - "(INTVAL (operands[3]) & 63) == 63" - "@ - sra\t%0,<1>%Y2 - sra\t%0,%1,%Y2" - [(set_attr "op_type" "RS,RSY") - (set_attr "atype" "reg,reg") - (set_attr "cpu_facility" "*,z196") - (set_attr "z10prop" "z10_super_E1,*")]) + [(set_attr "op_type" "RS,RS,RSY,RSY") + (set_attr "atype" "reg") + (set_attr "cpu_facility" "*,*,z196,z196") + (set_attr "enabled" "*,,*,") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) ;; diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md index 8443c69..1e2b1ba 100644 --- a/gcc/config/s390/subst.md +++ b/gcc/config/s390/subst.md @@ -65,3 +65,64 @@ ; Use this in the insn name. (define_subst_attr "masked_op" "masked_op_subst" "" "_and") + + +; This is like the addr_style_op substitution above but with a CC clobber. +(define_subst "addr_style_op_cc_subst" + [(set (match_operand:DSI 0 "" "") + (ashiftrt:DSI (match_operand:DSI 1 "" "") + (match_operand:SI 2 "" ""))) + (clobber (reg:CC CC_REGNUM))] + "REG_P (operands[2])" + [(set (match_dup 0) + (ashiftrt:DSI (match_dup 1) + (plus:SI (match_dup 2) + (match_operand 3 "const_int_operand" "n")))) + (clobber (reg:CC CC_REGNUM))]) + +(define_subst_attr "addr_style_op_cc" "addr_style_op_cc_subst" "" "_plus") +(define_subst_attr "addr_style_op_cc_enabled" "addr_style_op_cc_subst" "*" "0") +(define_subst_attr "addr_style_op_cc_op3" "addr_style_op_cc_subst" "0" "%Y3") + + +; This is like the masked_op substitution but with a CC clobber. +(define_subst "masked_op_cc_subst" + [(set (match_operand:DSI 0 "" "") + (ashiftrt:DSI (match_operand:DSI 1 "" "") + (match_operand:SI 2 "" ""))) + (clobber (reg:CC CC_REGNUM))] + "" + [(set (match_dup 0) + (ashiftrt:DSI (match_dup 1) + (and:SI (match_dup 2) + (match_operand:SI 3 "const_int_6bitset_operand" "")))) + (clobber (reg:CC CC_REGNUM))]) +(define_subst_attr "masked_op_cc" "masked_op_cc_subst" "" "_and") + + +; This adds an explicit CC reg set to an operation while keeping the +; set for the operation result as well. +(define_subst "setcc_subst" + [(set (match_operand:DSI 0 "" "") + (match_operand:DSI 1 "" "")) + (clobber (reg:CC CC_REGNUM))] + "s390_match_ccmode(insn, CCSmode)" + [(set (reg CC_REGNUM) + (compare (match_dup 1) (const_int 0))) + (set (match_dup 0) (match_dup 1))]) + +; Use this in the insn name. +(define_subst_attr "setcc" "setcc_subst" "" "_cc") + +; This adds an explicit CC reg set to an operation while dropping the +; result of the operation. +(define_subst "cconly_subst" + [(set (match_operand:DSI 0 "" "") + (match_operand:DSI 1 "" "")) + (clobber (reg:CC CC_REGNUM))] + "s390_match_ccmode(insn, CCSmode)" + [(set (reg CC_REGNUM) + (compare (match_dup 1) (const_int 0))) + (clobber (match_scratch:DSI 0 "=d,d,d,d"))]) + +(define_subst_attr "cconly" "cconly_subst" "" "_cconly")