From patchwork Tue Feb 23 14:33:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 586885 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 26C6C140779 for ; Wed, 24 Feb 2016 01:35:28 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=koQaDkSL; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=MBfDTwBCAxh/prid5ENpNUMvPIvyGztRguTukCtwHyGJeFTHYam29 nVIUDP2nOXnPaS2DmGBHwzcKb0cDPAl4zc5IxMpQsSkKvZNJGs1gNyE0D26y8LMO 1o2rswHo+J3nz2K/M0Mj2c+yMBIQjCA38jUFloL3wDAAZ0wEL9GAJU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; s=default; bh=+VX7BF6wFJ6JIfCcXORR72V9pFI=; b=koQaDkSLiMC9cWquReekM38kHkyl 8qAkNQFx/k5taL9ZLifdYCNfZejyO9vOX39Hzb52jeSUhS7OWR5WQhYh+Zz+DdcK S8aUTyO7HC3IsWhkOYhzjBUSYvYvmt2dEu+hRTwzzIKHXl3Nv59WVp1+24tIZhZi joRTHybO2AoREEU= Received: (qmail 21296 invoked by alias); 23 Feb 2016 14:33:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 21098 invoked by uid 89); 23 Feb 2016 14:33:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.1 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=krebbel, Krebbel, an, substitution X-HELO: e06smtp13.uk.ibm.com Received: from e06smtp13.uk.ibm.com (HELO e06smtp13.uk.ibm.com) (195.75.94.109) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Tue, 23 Feb 2016 14:33:32 +0000 Received: from localhost by e06smtp13.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Date: Tue, 23 Feb 2016 15:33:18 +0100 Message-Id: <1456238004-21150-4-git-send-email-krebbel@linux.vnet.ibm.com> In-Reply-To: <1456238004-21150-1-git-send-email-krebbel@linux.vnet.ibm.com> References: <1456238004-21150-1-git-send-email-krebbel@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16022314-0013-0000-0000-000008BCD8C6 X-IsSubscribed: yes This patch introduces substitution patterns to add PLUS const_int, and AND operands to patterns and uses this to rewrite the existing rotate pattern. gcc/ChangeLog: * config/s390/predicates.md (const_int_6bitset_operand): New predicates. * config/s390/s390.md: Include subst.md. ("rotl3"): New expander. ("rotl3", "*rotl3_and"): Merge insn definitions into ... ("*rotl3"): New insn definition. * config/s390/subst.md: New file. --- gcc/config/s390/predicates.md | 4 +++ gcc/config/s390/s390.c | 23 +++++++++++---- gcc/config/s390/s390.md | 34 +++++++++++----------- gcc/config/s390/subst.md | 67 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+), 23 deletions(-) create mode 100644 gcc/config/s390/subst.md diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md index cbc8092..9e91b5c 100644 --- a/gcc/config/s390/predicates.md +++ b/gcc/config/s390/predicates.md @@ -115,6 +115,10 @@ return true; }) +; An integer operand with the lowest order 6 bit all ones. +(define_predicate "const_int_6bitset_operand" + (and (match_code "const_int") + (match_test "(INTVAL (op) & 63) == 63"))) (define_predicate "nonzero_shift_count_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)"))) diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index cd53b15..43219dd 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -2994,18 +2994,18 @@ s390_decompose_address (rtx addr, struct s390_address *out) bool s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset) { - HOST_WIDE_INT off = 0; + rtx off = NULL_RTX; /* We can have an integer constant, an address register, or a sum of the two. */ - if (GET_CODE (op) == CONST_INT) + if (CONST_SCALAR_INT_P (op)) { - off = INTVAL (op); + off = op; op = NULL_RTX; } - if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT) + if (op && GET_CODE (op) == PLUS && CONST_SCALAR_INT_P (XEXP (op, 1))) { - off = INTVAL (XEXP (op, 1)); + off = XEXP (op, 1); op = XEXP (op, 0); } while (op && GET_CODE (op) == SUBREG) @@ -3015,7 +3015,18 @@ s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset) return false; if (offset) - *offset = off; + { + if (off == NULL_RTX) + *offset = 0; + else if (CONST_INT_P (off)) + *offset = INTVAL (off); + else if (CONST_WIDE_INT_P (off)) + /* The offset will anyway be cut down to 12 bits so take just + the lowest order chunk of the wide int. */ + *offset = CONST_WIDE_INT_ELT (off, 0); + else + gcc_unreachable (); + } if (base) *base = op; diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index b878ec2..9703a30 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -741,6 +741,8 @@ (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")]) +;; Subst pattern definitions +(include "subst.md") (include "vector.md") @@ -8360,28 +8362,26 @@ ; rotl(di|si)3 instruction pattern(s). ; -; rll, rllg -(define_insn "rotl3" - [(set (match_operand:GPR 0 "register_operand" "=d") - (rotate:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] +(define_expand "rotl3" + [(set (match_operand:GPR 0 "register_operand" "") + (rotate:GPR (match_operand:GPR 1 "register_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")))] "TARGET_CPU_ZARCH" - "rll\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") - (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + "") ; rll, rllg -(define_insn "*rotl3_and" - [(set (match_operand:GPR 0 "register_operand" "=d") - (rotate:GPR (match_operand:GPR 1 "register_operand" "d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))))] - "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" - "rll\t%0,%1,%Y2" +(define_insn "*rotl3" + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (rotate:GPR (match_operand:GPR 1 "register_operand" "d,d") + (match_operand:SI 2 "nonmemory_operand" "a,n")))] + "TARGET_CPU_ZARCH" + "@ + rll\t%0,%1,(%2) + rll\t%0,%1,%Y2" [(set_attr "op_type" "RSE") (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + (set_attr "enabled" "*,") + (set_attr "z10prop" "z10_super_E1")]) ;; diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md new file mode 100644 index 0000000..8443c69 --- /dev/null +++ b/gcc/config/s390/subst.md @@ -0,0 +1,67 @@ +;;- Machine description for GNU compiler -- S/390 / zSeries version. +;; Subst patterns. +;; Copyright (C) 2016 Free Software Foundation, Inc. +;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it under +;; the terms of the GNU General Public License as published by the Free +;; Software Foundation; either version 3, or (at your option) any later +;; version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY +;; WARRANTY; without even the implied warranty of MERCHANTABILITY or +;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +;; for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_code_iterator SUBST [ashift lshiftrt rotate]) + +; This expands an register/immediate operand to a register+immediate +; operand to draw advantage of the address style operand format +; providing a addition for free. +(define_subst "addr_style_op_subst" + [(set (match_operand:DSI 0 "" "") + (SUBST:DSI (match_operand:DSI 1 "" "") + (match_operand:SI 2 "" "")))] + "" + [(set (match_dup 0) + (SUBST:DSI (match_dup 1) + (plus:SI (match_operand:SI 2 "register_operand" "a") + (match_operand 3 "const_int_operand" "n"))))]) + +; Use this in the insn name. +(define_subst_attr "addr_style_op" "addr_style_op_subst" "" "_plus") + +; In the subst pattern the additional const int operand will be used +; as displacement. In the normal version the displacements stays just +; 0. +(define_subst_attr "addr_style_op_op3" "addr_style_op_subst" "0" "%Y3") + +; The constraints for the second alternative are ok. However, the +; output template is not. We simply disable the alternative. +; Alternatively we could also adjust the output template with a +; subst_attr. +(define_subst_attr "addr_style_op_enabled" "addr_style_op_subst" "*" "0") + + +; This substitution adds an explicit AND operation to the second +; operand. This way previous operations on the now masked out bits +; might get optimized away. +(define_subst "masked_op_subst" + [(set (match_operand:DSI 0 "" "") + (SUBST:DSI (match_operand:DSI 1 "" "") + (match_operand:SI 2 "" "")))] + "" + [(set (match_dup 0) + (SUBST:DSI (match_dup 1) + (and:SI (match_dup 2) + (match_operand:SI 3 "const_int_6bitset_operand" ""))))]) + +; Use this in the insn name. +(define_subst_attr "masked_op" "masked_op_subst" "" "_and") +