From patchwork Tue Feb 23 14:33:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 586880 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 35DD1140778 for ; Wed, 24 Feb 2016 01:34:07 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=i4JcgbQ2; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=qN6sQWqC+KsM6Ar6shFhldtXBAIqxi/WeHepBZqEgcfwiQknTpZSe 08QVOpoTvKf7jbB+vPu3AaPVMubbTOh+B6V3Eu/s9c9gr0Cf4jAGq2ay/P7nRT8i HyMXDO9Fn0tu3ZrGsLa/WSYb2vce73EotOBe45vCVyojx3N4R/ly8E= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; s=default; bh=FKBVmWEGZRIMXTYR3ekKLRCET4U=; b=i4JcgbQ2ClS9+yfJqncHybe96EC/ 1LjPhW1puO4YBuSwTd/hZ6CUt2P6IiS7jvLHv4oCryUAYKe9UMRTDxEEiR5pmdCi +NvwUiIVJ3/NnLSmbk9eKTKeURryZXcx0SjSNvotrq6By1qnjug6ibNi5UuiRTDf wgfDKgyVeAMnCTo= Received: (qmail 19919 invoked by alias); 23 Feb 2016 14:33:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 19836 invoked by uid 89); 23 Feb 2016 14:33:37 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.1 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=Square, fff, fma, Length X-HELO: e06smtp14.uk.ibm.com Received: from e06smtp14.uk.ibm.com (HELO e06smtp14.uk.ibm.com) (195.75.94.110) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Tue, 23 Feb 2016 14:33:31 +0000 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 23 Feb 2016 14:33:28 -0000 Received: from d06dlp03.portsmouth.uk.ibm.com (9.149.20.15) by e06smtp14.uk.ibm.com (192.168.101.144) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Tue, 23 Feb 2016 14:33:25 -0000 X-IBM-Helo: d06dlp03.portsmouth.uk.ibm.com X-IBM-MailFrom: krebbel@linux.vnet.ibm.com X-IBM-RcptTo: gcc-patches@gcc.gnu.org Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by d06dlp03.portsmouth.uk.ibm.com (Postfix) with ESMTP id A95EC1B08067 for ; Tue, 23 Feb 2016 14:33:44 +0000 (GMT) Received: from d06av09.portsmouth.uk.ibm.com (d06av09.portsmouth.uk.ibm.com [9.149.37.250]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u1NEXPlm60424438 for ; Tue, 23 Feb 2016 14:33:25 GMT Received: from d06av09.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av09.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u1NEXOBx023530 for ; Tue, 23 Feb 2016 07:33:24 -0700 Received: from maggie.boeblingen.de.ibm.com (dyn-9-152-212-123.boeblingen.de.ibm.com [9.152.212.123]) by d06av09.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u1NEXOE6023504 (version=TLSv1/SSLv3 cipher=AES256-SHA256 bits=256 verify=NO) for ; Tue, 23 Feb 2016 07:33:24 -0700 From: Andreas Krebbel To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/9] S/390: Use enabled attribute overrides to disable alternatives. Date: Tue, 23 Feb 2016 15:33:17 +0100 Message-Id: <1456238004-21150-3-git-send-email-krebbel@linux.vnet.ibm.com> In-Reply-To: <1456238004-21150-1-git-send-email-krebbel@linux.vnet.ibm.com> References: <1456238004-21150-1-git-send-email-krebbel@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16022314-0017-0000-0000-00000748693C X-IsSubscribed: yes So far whenever we wanted to disable an alternative we have used mode attributes emitting constraints matching an earlier alternative assuming that due to this the later alternative will never be chosen. With this patch the `enabled' attribute, which so far is only set from `cpu_facility', is overridden to 0 to disable certain alternatives. This comes handy when defining the substitutions later and while adding it anyway I've used it for the existing cases as well. gcc/ChangeLog: * config/s390/s390.md ("op_type", "atype", "length" attributes): Remove RRR type. It doesn't really exist. ("RRer", "f0", "v0", "vf", "vd", "op1", "Rf"): Remove mode attributes. ("BFP", "DFP", "nDSF", "nDFDI"): Add mode attributes. ("*cmp_ccs", "floatdi2", "add3") ("*add3_cc", "*add3_cconly", "sub3") ("*sub3_cc", "*sub3_cconly", "mul3") ("fma4", "fms4", "div3", "*neg2") ("*abs2", "*negabs2", "sqrt2"): Override `enabled' attribute. --- gcc/config/s390/s390.md | 215 +++++++++++++++++++++++++----------------------- 1 file changed, 111 insertions(+), 104 deletions(-) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 2c90eae..b878ec2 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -366,7 +366,7 @@ ;; Used to determine defaults for length and other attribute values. (define_attr "op_type" - "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX" + "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX" (const_string "NN")) ;; Instruction type attribute used for scheduling. @@ -393,7 +393,7 @@ ;; reg: Instruction does not use the agen unit (define_attr "atype" "agen,reg" - (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR") + (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") (const_string "reg") (const_string "agen"))) @@ -434,8 +434,8 @@ ;; Length in bytes. (define_attr "length" "" - (cond [(eq_attr "op_type" "E,RR") (const_int 2) - (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] + (cond [(eq_attr "op_type" "E,RR") (const_int 2) + (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] (const_int 6))) @@ -618,27 +618,14 @@ ;; fp register operands. The following attributes allow to merge the bfp and ;; dfp variants in a single insn definition. -;; This attribute is used to set op_type accordingly. -(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") - (DD "RRR") (SD "RRR")]) - -;; This attribute is used in the operand constraint list in order to have the -;; first and the second operand match for bfp modes. -(define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) - -;; This attribute is used to merge the scalar vector instructions into -;; the FP patterns. For non-supported modes (all but DF) it expands -;; to constraints which are supposed to be matched by an earlier -;; variant. -(define_mode_attr v0 [(TF "0") (DF "v") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "v") (SI "0")]) -(define_mode_attr vf [(TF "f") (DF "v") (SF "f") (TD "f") (DD "f") (DD "f") (TI "f") (DI "v") (SI "f")]) -(define_mode_attr vd [(TF "d") (DF "v") (SF "d") (TD "d") (DD "d") (DD "d") (TI "d") (DI "v") (SI "d")]) - -;; This attribute is used in the operand list of the instruction to have an -;; additional operand for the dfp instructions. -(define_mode_attr op1 [(TF "") (DF "") (SF "") - (TD "%1,") (DD "%1,") (SD "%1,")]) - +;; These mode attributes are supposed to be used in the `enabled' insn +;; attribute to disable certain alternatives for certain modes. +(define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) +(define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) +(define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) +(define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") + (TD "0") (DD "0") (DD "0") + (TI "0") (DI "*") (SI "0")]) ;; This attribute is used in the operand constraint list ;; for instructions dealing with the sign bit of 32 or 64bit fp values. @@ -648,10 +635,6 @@ ;; target operand uses the same fp register. (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) -;; In FP templates, "" will expand to "f" in TFmode and "R" otherwise. -;; This is used to disable the memory alternative in TFmode patterns. -(define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) - ;; This attribute adds b for bfp instructions and t for dfp instructions and is used ;; within instruction mnemonics. (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) @@ -1260,13 +1243,14 @@ (define_insn "*cmp_ccs" [(set (reg CC_REGNUM) (compare (match_operand:FP 0 "register_operand" "f,f") - (match_operand:FP 1 "general_operand" "f,")))] + (match_operand:FP 1 "general_operand" "f,R")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" "@ cr\t%0,%1 cb\t%0,%1" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimp")]) + (set_attr "type" "fsimp") + (set_attr "enabled" "*,")]) ; wfcedbs, wfchdbs, wfchedbs (define_insn "*vec_cmpdf_cconly" @@ -4715,15 +4699,16 @@ ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr (define_insn "floatdi2" - [(set (match_operand:FP 0 "register_operand" "=f,") - (float:FP (match_operand:DI 1 "register_operand" "d,")))] + [(set (match_operand:FP 0 "register_operand" "=f,v") + (float:FP (match_operand:DI 1 "register_operand" "d,v")))] "TARGET_ZARCH && TARGET_HARD_FLOAT" "@ cgr\t%0,%1 wcdgb\t%v0,%v1,0,0" [(set_attr "op_type" "RRE,VRR") (set_attr "type" "itof" ) - (set_attr "cpu_facility" "*,vec")]) + (set_attr "cpu_facility" "*,vec") + (set_attr "enabled" "*,")]) ; cxfbr, cdfbr, cefbr (define_insn "floatsi2" @@ -5482,47 +5467,53 @@ ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr ; FIXME: wfadb does not clobber cc (define_insn "add3" - [(set (match_operand:FP 0 "register_operand" "=f, f,") - (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%, 0,") - (match_operand:FP 2 "general_operand" "f,,"))) + [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") + (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v") + (match_operand:FP 2 "general_operand" "f,f,R,v"))) (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT" "@ - ar\t%0,%2 + atr\t%0,%1,%2 + abr\t%0,%2 ab\t%0,%2 wfadb\t%v0,%v1,%v2" - [(set_attr "op_type" ",RXE,VRR") + [(set_attr "op_type" "RRF,RRE,RXE,VRR") (set_attr "type" "fsimp") - (set_attr "cpu_facility" "*,*,vec")]) + (set_attr "cpu_facility" "*,*,*,vec") + (set_attr "enabled" ",,,")]) ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr (define_insn "*add3_cc" [(set (reg CC_REGNUM) - (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%,0") - (match_operand:FP 2 "general_operand" " f,")) + (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") + (match_operand:FP 2 "general_operand" "f,f,R")) (match_operand:FP 3 "const0_operand" ""))) - (set (match_operand:FP 0 "register_operand" "=f,f") + (set (match_operand:FP 0 "register_operand" "=f,f,f") (plus:FP (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" "@ - ar\t%0,%2 + atr\t%0,%1,%2 + abr\t%0,%2 ab\t%0,%2" - [(set_attr "op_type" ",RXE") - (set_attr "type" "fsimp")]) + [(set_attr "op_type" "RRF,RRE,RXE") + (set_attr "type" "fsimp") + (set_attr "enabled" ",,")]) ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr (define_insn "*add3_cconly" [(set (reg CC_REGNUM) - (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%,0") - (match_operand:FP 2 "general_operand" " f,")) + (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") + (match_operand:FP 2 "general_operand" "f,f,R")) (match_operand:FP 3 "const0_operand" ""))) - (clobber (match_scratch:FP 0 "=f,f"))] + (clobber (match_scratch:FP 0 "=f,f,f"))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" "@ - ar\t%0,%2 + atr\t%0,%1,%2 + abr\t%0,%2 ab\t%0,%2" - [(set_attr "op_type" ",RXE") - (set_attr "type" "fsimp")]) + [(set_attr "op_type" "RRF,RRE,RXE") + (set_attr "type" "fsimp") + (set_attr "enabled" ",,")]) ; ; Pointer add instruction patterns @@ -5906,47 +5897,53 @@ ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr (define_insn "sub3" - [(set (match_operand:FP 0 "register_operand" "=f, f,") - (minus:FP (match_operand:FP 1 "register_operand" ", 0,") - (match_operand:FP 2 "general_operand" "f,,"))) + [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") + (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v") + (match_operand:FP 2 "general_operand" "f,f,R,v"))) (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT" "@ - sr\t%0,%2 + str\t%0,%1,%2 + sbr\t%0,%2 sb\t%0,%2 wfsdb\t%v0,%v1,%v2" - [(set_attr "op_type" ",RXE,VRR") + [(set_attr "op_type" "RRF,RRE,RXE,VRR") (set_attr "type" "fsimp") - (set_attr "cpu_facility" "*,*,vec")]) + (set_attr "cpu_facility" "*,*,*,vec") + (set_attr "enabled" ",,,")]) ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr (define_insn "*sub3_cc" [(set (reg CC_REGNUM) - (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" ",0") - (match_operand:FP 2 "general_operand" "f,")) + (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") + (match_operand:FP 2 "general_operand" "f,f,R")) (match_operand:FP 3 "const0_operand" ""))) - (set (match_operand:FP 0 "register_operand" "=f,f") + (set (match_operand:FP 0 "register_operand" "=f,f,f") (minus:FP (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" "@ - sr\t%0,%2 + str\t%0,%1,%2 + sbr\t%0,%2 sb\t%0,%2" - [(set_attr "op_type" ",RXE") - (set_attr "type" "fsimp")]) + [(set_attr "op_type" "RRF,RRE,RXE") + (set_attr "type" "fsimp") + (set_attr "enabled" ",,")]) ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr (define_insn "*sub3_cconly" [(set (reg CC_REGNUM) - (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" ",0") - (match_operand:FP 2 "general_operand" "f,")) + (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") + (match_operand:FP 2 "general_operand" "f,f,R")) (match_operand:FP 3 "const0_operand" ""))) - (clobber (match_scratch:FP 0 "=f,f"))] + (clobber (match_scratch:FP 0 "=f,f,f"))] "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" "@ - sr\t%0,%2 + str\t%0,%1,%2 + sbr\t%0,%2 sb\t%0,%2" - [(set_attr "op_type" ",RXE") - (set_attr "type" "fsimp")]) + [(set_attr "op_type" "RRF,RRE,RXE") + (set_attr "type" "fsimp") + (set_attr "enabled" ",,")]) ;; @@ -6328,24 +6325,26 @@ ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr (define_insn "mul3" - [(set (match_operand:FP 0 "register_operand" "=f, f,") - (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%, 0,") - (match_operand:FP 2 "general_operand" "f,,")))] + [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") + (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v") + (match_operand:FP 2 "general_operand" "f,f,R,v")))] "TARGET_HARD_FLOAT" "@ - mr\t%0,%2 + mtr\t%0,%1,%2 + mbr\t%0,%2 mb\t%0,%2 wfmdb\t%v0,%v1,%v2" - [(set_attr "op_type" ",RXE,VRR") + [(set_attr "op_type" "RRF,RRE,RXE,VRR") (set_attr "type" "fmul") - (set_attr "cpu_facility" "*,*,vec")]) + (set_attr "cpu_facility" "*,*,*,vec") + (set_attr "enabled" ",,,")]) ; madbr, maebr, maxb, madb, maeb (define_insn "fma4" - [(set (match_operand:DSF 0 "register_operand" "=f,f,") - (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,") - (match_operand:DSF 2 "nonimmediate_operand" "f,R,") - (match_operand:DSF 3 "register_operand" "0,0,")))] + [(set (match_operand:DSF 0 "register_operand" "=f,f,v") + (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v") + (match_operand:DSF 2 "nonimmediate_operand" "f,R,v") + (match_operand:DSF 3 "register_operand" "0,0,v")))] "TARGET_HARD_FLOAT" "@ mabr\t%0,%1,%2 @@ -6353,14 +6352,15 @@ wfmadb\t%v0,%v1,%v2,%v3" [(set_attr "op_type" "RRE,RXE,VRR") (set_attr "type" "fmadd") - (set_attr "cpu_facility" "*,*,vec")]) + (set_attr "cpu_facility" "*,*,vec") + (set_attr "enabled" "*,*,")]) ; msxbr, msdbr, msebr, msxb, msdb, mseb (define_insn "fms4" - [(set (match_operand:DSF 0 "register_operand" "=f,f,") - (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,") - (match_operand:DSF 2 "nonimmediate_operand" "f,R,") - (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,"))))] + [(set (match_operand:DSF 0 "register_operand" "=f,f,v") + (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v") + (match_operand:DSF 2 "nonimmediate_operand" "f,R,v") + (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v"))))] "TARGET_HARD_FLOAT" "@ msbr\t%0,%1,%2 @@ -6368,7 +6368,8 @@ wfmsdb\t%v0,%v1,%v2,%v3" [(set_attr "op_type" "RRE,RXE,VRR") (set_attr "type" "fmadd") - (set_attr "cpu_facility" "*,*,vec")]) + (set_attr "cpu_facility" "*,*,vec") + (set_attr "enabled" "*,*,")]) ;; ;;- Divide and modulo instructions. @@ -6794,17 +6795,19 @@ ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr (define_insn "div3" - [(set (match_operand:FP 0 "register_operand" "=f, f,") - (div:FP (match_operand:FP 1 "register_operand" ", 0,") - (match_operand:FP 2 "general_operand" "f,,")))] + [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") + (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v") + (match_operand:FP 2 "general_operand" "f,f,R,v")))] "TARGET_HARD_FLOAT" "@ - dr\t%0,%2 + dtr\t%0,%1,%2 + dbr\t%0,%2 db\t%0,%2 wfddb\t%v0,%v1,%v2" - [(set_attr "op_type" ",RXE,VRR") + [(set_attr "op_type" "RRF,RRE,RXE,VRR") (set_attr "type" "fdiv") - (set_attr "cpu_facility" "*,*,vec")]) + (set_attr "cpu_facility" "*,*,*,vec") + (set_attr "enabled" ",,,")]) ;; @@ -8015,8 +8018,8 @@ ; lcxbr, lcdbr, lcebr ; FIXME: wflcdb does not clobber cc (define_insn "*neg2" - [(set (match_operand:BFP 0 "register_operand" "=f,") - (neg:BFP (match_operand:BFP 1 "register_operand" "f,"))) + [(set (match_operand:BFP 0 "register_operand" "=f,v") + (neg:BFP (match_operand:BFP 1 "register_operand" "f,v"))) (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT" "@ @@ -8024,7 +8027,8 @@ wflcdb\t%0,%1" [(set_attr "op_type" "RRE,VRR") (set_attr "cpu_facility" "*,vec") - (set_attr "type" "fsimp,*")]) + (set_attr "type" "fsimp,*") + (set_attr "enabled" "*,")]) ;; @@ -8137,8 +8141,8 @@ ; lpxbr, lpdbr, lpebr ; FIXME: wflpdb does not clobber cc (define_insn "*abs2" - [(set (match_operand:BFP 0 "register_operand" "=f,") - (abs:BFP (match_operand:BFP 1 "register_operand" "f,"))) + [(set (match_operand:BFP 0 "register_operand" "=f,v") + (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT" "@ @@ -8146,7 +8150,8 @@ wflpdb\t%0,%1" [(set_attr "op_type" "RRE,VRR") (set_attr "cpu_facility" "*,vec") - (set_attr "type" "fsimp,*")]) + (set_attr "type" "fsimp,*") + (set_attr "enabled" "*,")]) ;; @@ -8252,8 +8257,8 @@ ; lnxbr, lndbr, lnebr ; FIXME: wflndb does not clobber cc (define_insn "*negabs2" - [(set (match_operand:BFP 0 "register_operand" "=f,") - (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,")))) + [(set (match_operand:BFP 0 "register_operand" "=f,v") + (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT" "@ @@ -8261,7 +8266,8 @@ wflndb\t%0,%1" [(set_attr "op_type" "RRE,VRR") (set_attr "cpu_facility" "*,vec") - (set_attr "type" "fsimp,*")]) + (set_attr "type" "fsimp,*") + (set_attr "enabled" "*,")]) ;; ;;- Square root instructions. @@ -8273,8 +8279,8 @@ ; sqxbr, sqdbr, sqebr, sqdb, sqeb (define_insn "sqrt2" - [(set (match_operand:BFP 0 "register_operand" "=f, f,") - (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,,")))] + [(set (match_operand:BFP 0 "register_operand" "=f,f,v") + (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] "TARGET_HARD_FLOAT" "@ sqbr\t%0,%1 @@ -8282,7 +8288,8 @@ wfsqdb\t%v0,%v1" [(set_attr "op_type" "RRE,RXE,VRR") (set_attr "type" "fsqrt") - (set_attr "cpu_facility" "*,*,vec")]) + (set_attr "cpu_facility" "*,*,vec") + (set_attr "enabled" "*,,")]) ;;