From patchwork Thu Jan 14 16:33:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 567684 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1CE101409A0 for ; Fri, 15 Jan 2016 08:06:28 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=CdYDqMdf; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=WvTRexRzrKnxdpSasHCs3C/xvEXLAfGnFmPsKjk5WQXgZfGQVJFKn 6gauHD3/3wMXc+zxgKePxr+hjgUujD0B1WBm+JgQ4OQ4QaP2znLElor0AsrtEVR/ /YMRr8haCaz3a/64NnfHQ177Ruu2rpr0Qmswh8eOEQusN72/9IeZr0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; s=default; bh=GiS5ARmqAKA4D2T7kkzYnQlMz+4=; b=CdYDqMdfAXpl85OFUePUYDOzSSUo pxUKL13nhb3bbX8x7bYeurnDt9qXx4X2pixKLKNSRflZc39HW6oNjABTylHtB0zw C0bVr9sdtPn/lHoaLWMNVZq7/nE8LEr6kYMoICJjpHcVfIZ4Y+4hsS3VsT2MzMV2 bQOUjezqh0HrU+A= Received: (qmail 73103 invoked by alias); 14 Jan 2016 21:06:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 73092 invoked by uid 89); 14 Jan 2016 21:06:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.7 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=krebbel@linux.vnet.ibm.com, krebbellinuxvnetibmcom, sk:krebbel, U*krebbel X-HELO: e06smtp05.uk.ibm.com Received: from e06smtp05.uk.ibm.com (HELO e06smtp05.uk.ibm.com) (195.75.94.101) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Thu, 14 Jan 2016 21:06:20 +0000 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Date: Thu, 14 Jan 2016 17:33:29 +0100 Message-Id: <1452789254-12603-5-git-send-email-krebbel@linux.vnet.ibm.com> In-Reply-To: <1452789254-12603-1-git-send-email-krebbel@linux.vnet.ibm.com> References: <1452789254-12603-1-git-send-email-krebbel@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16011421-0021-0000-0000-000005749E01 X-IsSubscribed: yes With this patch the substitution patterns added earlier are used for the logical right shift and all the left shift patterns. 2016-01-14 Andreas Krebbel * config/s390/s390.md ("*di3_31", "*3") ("*di3_31_and", "*3_and"): Merge into single pattern definition ... ("*di3_31"): New pattern. --- gcc/config/s390/s390.md | 61 ++++++++++++++++++------------------------------- 1 file changed, 22 insertions(+), 39 deletions(-) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 3ed10f4..8a99cd1 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -8389,56 +8389,39 @@ "" "") +; ESA 64 bit register pair shift with reg or imm shift count ; sldl, srdl -(define_insn "*di3_31" - [(set (match_operand:DI 0 "register_operand" "=d") - (SHIFT:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] +(define_insn "*di3_31" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (SHIFT:DI (match_operand:DI 1 "register_operand" "0,0") + (match_operand:SI 2 "addrreg_or_constint_operand" "a,n")))] "!TARGET_ZARCH" - "sdl\t%0,%Y2" + "@ + sdl\t%0,(%2) + sdl\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg") + (set_attr "disabled" "0,") (set_attr "z196prop" "z196_cracked")]) -; sll, srl, sllg, srlg, sllk, srlk -(define_insn "*3" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (SHIFT:GPR (match_operand:GPR 1 "register_operand" ",d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] - "" - "@ - sl\t%0,<1>%Y2 - sl\t%0,%1,%Y2" - [(set_attr "op_type" "RS,RSY") - (set_attr "atype" "reg,reg") - (set_attr "cpu_facility" "*,z196") - (set_attr "z10prop" "z10_super_E1,*")]) - -; sldl, srdl -(define_insn "*di3_31_and" - [(set (match_operand:DI 0 "register_operand" "=d") - (SHIFT:DI (match_operand:DI 1 "register_operand" "0") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))))] - "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" - "sdl\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) +; 64 bit register shift with reg or imm shift count ; sll, srl, sllg, srlg, sllk, srlk -(define_insn "*3_and" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (SHIFT:GPR (match_operand:GPR 1 "register_operand" ",d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") - (match_operand:SI 3 "const_int_operand" "n,n"))))] - "(INTVAL (operands[3]) & 63) == 63" +(define_insn "*3" + [(set (match_operand:GPR 0 "register_operand" "=d, d,d,d") + (SHIFT:GPR (match_operand:GPR 1 "register_operand" ",,d,d") + (match_operand:SI 2 "addrreg_or_constint_operand" "a, n,a,n")))] + "" "@ + sl\t%0,<1>(%2) sl\t%0,<1>%Y2 + sl\t%0,%1,(%2) sl\t%0,%1,%Y2" - [(set_attr "op_type" "RS,RSY") - (set_attr "atype" "reg,reg") - (set_attr "cpu_facility" "*,z196") - (set_attr "z10prop" "z10_super_E1,*")]) + [(set_attr "op_type" "RS,RS,RSY,RSY") + (set_attr "atype" "reg,reg,reg,reg") + (set_attr "cpu_facility" "*,*,z196,z196") + (set_attr "disabled" "0,,0,") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) ; ; ashr(di|si)3 instruction pattern(s).