From patchwork Thu Jan 14 16:33:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 567595 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0F9C81402A8 for ; Fri, 15 Jan 2016 03:37:12 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=TrmoE8Y2; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=XTXwzQW+gJw8S/u1eAi1unCpLjLVBIO6xYeDvybpdiaUKlWM2lwdC YD+YUnlKkDN8bD6AHvBAaRTxskA7NaxZGOk+sO3Zgg0JN9bVZyPytj4b7mhoZ4tw S80dXNV+7Z0Mv+EiCgkFABGox20MlBhKHNbZMx4m2Ch12x6Fn2vHJk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; s=default; bh=4ldi1Z3rler98nOuPesPLmZU2M0=; b=TrmoE8Y28LitHAh2bG7qpSe3Mtrj Mu7D39ln+5XaPKV5v3fKuVzag1+PBExWVZ3Gy/oa2iRPXDUnO4Ir467eCFNfp1N4 bzPrIlikVgcMYeRWmH0X0JiA31XGDnoC7wWV85oiD16C0YT5BwAuUad2JRkQYeCk ny8mFu3JNxs4Jhc= Received: (qmail 62932 invoked by alias); 14 Jan 2016 16:36:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 62842 invoked by uid 89); 14 Jan 2016 16:36:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.9 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=dd, atype, UD:s390.md, s390md X-HELO: e06smtp15.uk.ibm.com Received: from e06smtp15.uk.ibm.com (HELO e06smtp15.uk.ibm.com) (195.75.94.111) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Thu, 14 Jan 2016 16:36:55 +0000 Received: from localhost by e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Date: Thu, 14 Jan 2016 17:33:28 +0100 Message-Id: <1452789254-12603-4-git-send-email-krebbel@linux.vnet.ibm.com> In-Reply-To: <1452789254-12603-1-git-send-email-krebbel@linux.vnet.ibm.com> References: <1452789254-12603-1-git-send-email-krebbel@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16011416-0021-0000-0000-000008961BEC X-IsSubscribed: yes This patch introduces substitution patterns to add PLUS const_int, and AND operands to patterns and uses this to rewrite the existing rotate pattern. gcc/ChangeLog: 2016-01-14 Andreas Krebbel * config/s390/predicates.md (addrreg_or_constint_operand) (const_int_6bitset_operand): New predicates. * config/s390/s390.md: Include subst.md. ("rotl3"): New expander. ("rotl3", "*rotl3_and"): Merge insn definitions into ... ("*rotl3"): New insn definition. * config/s390/subst.md: New file. --- gcc/config/s390/predicates.md | 25 ++++++++++++++++ gcc/config/s390/s390.md | 34 +++++++++++----------- gcc/config/s390/subst.md | 66 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+), 17 deletions(-) create mode 100644 gcc/config/s390/subst.md diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md index cbc8092..b58cb22 100644 --- a/gcc/config/s390/predicates.md +++ b/gcc/config/s390/predicates.md @@ -115,6 +115,31 @@ return true; }) +; Accept single register and immediate operands usable as shift +; counts. +(define_predicate "addrreg_or_constint_operand" + (match_code "reg, subreg, const_int") +{ + if (GET_MODE (op) != VOIDmode + && GET_MODE_CLASS (GET_MODE (op)) != MODE_INT) + return false; + + while (op && GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + if (REG_P (op) + && (REGNO (op) >= FIRST_PSEUDO_REGISTER || ADDR_REG_P (op))) + return true; + + if (CONST_INT_P (op)) + return true; + + return false; +}) +; An integer operand with the lowest order 6 bit all ones. +(define_predicate "const_int_6bitset_operand" + (and (match_code "const_int") + (match_test "(INTVAL (op) & 63) == 63"))) (define_predicate "nonzero_shift_count_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)"))) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 39467ad..3ed10f4 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -739,6 +739,8 @@ (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")]) +;; Subst pattern definitions +(include "subst.md") (include "vector.md") @@ -8350,28 +8352,26 @@ ; rotl(di|si)3 instruction pattern(s). ; -; rll, rllg -(define_insn "rotl3" - [(set (match_operand:GPR 0 "register_operand" "=d") - (rotate:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] +(define_expand "rotl3" + [(set (match_operand:GPR 0 "register_operand" "") + (rotate:GPR (match_operand:GPR 1 "register_operand" "") + (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] "TARGET_CPU_ZARCH" - "rll\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") - (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + "") ; rll, rllg -(define_insn "*rotl3_and" - [(set (match_operand:GPR 0 "register_operand" "=d") - (rotate:GPR (match_operand:GPR 1 "register_operand" "d") - (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") - (match_operand:SI 3 "const_int_operand" "n"))))] - "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" - "rll\t%0,%1,%Y2" +(define_insn "*rotl3" + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (rotate:GPR (match_operand:GPR 1 "register_operand" "d,d") + (match_operand:SI 2 "addrreg_or_constint_operand" "a,n")))] + "TARGET_CPU_ZARCH" + "@ + rll\t%0,%1,(%2) + rll\t%0,%1,%Y2" [(set_attr "op_type" "RSE") (set_attr "atype" "reg") - (set_attr "z10prop" "z10_super_E1")]) + (set_attr "disabled" "0,") + (set_attr "z10prop" "z10_super_E1")]) ;; diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md new file mode 100644 index 0000000..481f33e --- /dev/null +++ b/gcc/config/s390/subst.md @@ -0,0 +1,66 @@ +;;- Machine description for GNU compiler -- S/390 / zSeries version. +;; Subst patterns. +;; Copyright (C) 2016 Free Software Foundation, Inc. +;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it under +;; the terms of the GNU General Public License as published by the Free +;; Software Foundation; either version 3, or (at your option) any later +;; version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY +;; WARRANTY; without even the implied warranty of MERCHANTABILITY or +;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +;; for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_code_iterator SUBST [ashift lshiftrt rotate]) + +; This expands an register/immediate operand to a register+immediate +; operand to draw advantage of the address style operand format +; providing a addition for free. +(define_subst "addr_style_op_subst" + [(set (match_operand:DSI 0 "" "") + (SUBST:DSI (match_operand:DSI 1 "" "") + (match_operand:SI 2 "" "")))] + "REG_P (operands[2])" + [(set (match_dup 0) + (SUBST:DSI (match_dup 1) + (plus:SI (match_dup 2) + (match_operand 3 "const_int_operand" "n"))))]) + +; Use this in the insn name. +(define_subst_attr "addr_style_op" "addr_style_op_subst" "" "_plus") + +; In the subst pattern the additional const int operand will be used +; as displacement. In the normal version the displacements stays just +; 0. +(define_subst_attr "addr_style_op_op3" "addr_style_op_subst" "0" "%Y3") + +; In the subst pattern we have to disable the alternative where op2 is +; already a constant. This attribute is supposed to be used in the +; "disabled" insn attribute to achieve this. +(define_subst_attr "addr_style_op_disable" "addr_style_op_subst" "0" "1") + + +; This substitution adds an explicit AND operation to the second +; operand. This way previous operations on the now masked out bits +; might get optimized away. +(define_subst "masked_op_subst" + [(set (match_operand:DSI 0 "" "") + (SUBST:DSI (match_operand:DSI 1 "" "") + (match_operand:SI 2 "" "")))] + "" + [(set (match_dup 0) + (SUBST:DSI (match_dup 1) + (and:SI (match_dup 2) + (match_operand:SI 3 "const_int_6bitset_operand" ""))))]) + +; Use this in the insn name. +(define_subst_attr "masked_op" "masked_op_subst" "" "_and") +