diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index d6097c1..39467ad 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -357,7 +357,7 @@
 ;; Used to determine defaults for length and other attribute values.
 
 (define_attr "op_type"
-  "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
+  "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
   (const_string "NN"))
 
 ;; Instruction type attribute used for scheduling.
@@ -384,7 +384,7 @@
 ;;   reg: Instruction does not use the agen unit
 
 (define_attr "atype" "agen,reg"
-  (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
+  (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
 		(const_string "reg")
 		(const_string "agen")))
 
@@ -425,8 +425,8 @@
 ;; Length in bytes.
 
 (define_attr "length" ""
-  (cond [(eq_attr "op_type" "E,RR")		              (const_int 2)
-         (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR")  (const_int 4)]
+  (cond [(eq_attr "op_type" "E,RR")		          (const_int 2)
+         (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF")  (const_int 4)]
     (const_int 6)))
 
 
@@ -442,8 +442,18 @@
   "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
   (const_string "standard"))
 
+; Insn attribute with boolean value
+;  1 to disable an insn alternative
+;  0 or * for an active insn alternative
+;  an active alternative can still be disabled due to lacking cpu
+;  facility support
+(define_attr "disabled" "" (const_int 0))
+
 (define_attr "enabled" ""
-  (cond [(eq_attr "cpu_facility" "standard")
+  (cond [(eq_attr "disabled" "1")
+	 (const_int 0)
+
+	 (eq_attr "cpu_facility" "standard")
 	 (const_int 1)
 
          (and (eq_attr "cpu_facility" "ieee")
@@ -606,27 +616,14 @@
 ;; fp register operands.  The following attributes allow to merge the bfp and
 ;; dfp variants in a single insn definition.
 
-;; This attribute is used to set op_type accordingly.
-(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
-                        (DD "RRR") (SD "RRR")])
-
-;; This attribute is used in the operand constraint list in order to have the
-;; first and the second operand match for bfp modes.
-(define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
-
-;; This attribute is used to merge the scalar vector instructions into
-;; the FP patterns.  For non-supported modes (all but DF) it expands
-;; to constraints which are supposed to be matched by an earlier
-;; variant.
-(define_mode_attr v0      [(TF "0") (DF "v") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "v") (SI "0")])
-(define_mode_attr vf      [(TF "f") (DF "v") (SF "f") (TD "f") (DD "f") (DD "f") (TI "f") (DI "v") (SI "f")])
-(define_mode_attr vd      [(TF "d") (DF "v") (SF "d") (TD "d") (DD "d") (DD "d") (TI "d") (DI "v") (SI "d")])
-
-;; This attribute is used in the operand list of the instruction to have an
-;; additional operand for the dfp instructions.
-(define_mode_attr op1 [(TF "") (DF "") (SF "")
-                       (TD "%1,") (DD "%1,") (SD "%1,")])
-
+;; These mode attributes are supposed to be used in the `disabled' insn
+;; attribute to disable certain alternatives for certain modes.
+(define_mode_attr BFP [(TF "1") (DF "1") (SF "1") (TD "0") (DD "0") (DD "0")])
+(define_mode_attr DFP [(TF "0") (DF "0") (SF "0") (TD "1") (DD "1") (DD "1")])
+(define_mode_attr nDSF [(TF "1") (DF "0") (SF "0") (TD "1") (DD "1") (SD "1")])
+(define_mode_attr nDFDI [(TF "1") (DF "0") (SF "1")
+			 (TD "1") (DD "1") (DD "1")
+			 (TI "1") (DI "0") (SI "1")])
 
 ;; This attribute is used in the operand constraint list
 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
@@ -636,10 +633,6 @@
 ;; target operand uses the same fp register.
 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
 
-;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
-;; This is used to disable the memory alternative in TFmode patterns.
-(define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
-
 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
 ;; within instruction mnemonics.
 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
@@ -1248,13 +1241,14 @@
 (define_insn "*cmp<mode>_ccs"
   [(set (reg CC_REGNUM)
         (compare (match_operand:FP 0 "register_operand" "f,f")
-                 (match_operand:FP 1 "general_operand"  "f,<Rf>")))]
+                 (match_operand:FP 1 "general_operand"  "f,R")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
    c<xde><bt>r\t%0,%1
    c<xde>b\t%0,%1"
    [(set_attr "op_type" "RRE,RXE")
-    (set_attr "type"  "fsimp<mode>")])
+    (set_attr "type"  "fsimp<mode>")
+    (set_attr "disabled" "0,<nDSF>")])
 
 ; wfcedbs, wfchdbs, wfchedbs
 (define_insn "*vec_cmp<insn_cmp>df_cconly"
@@ -4695,15 +4689,16 @@
 
 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
 (define_insn "floatdi<mode>2"
-  [(set (match_operand:FP           0 "register_operand" "=f,<vf>")
-        (float:FP (match_operand:DI 1 "register_operand"  "d,<vd>")))]
+  [(set (match_operand:FP           0 "register_operand" "=f,v")
+        (float:FP (match_operand:DI 1 "register_operand"  "d,v")))]
   "TARGET_ZARCH && TARGET_HARD_FLOAT"
   "@
    c<xde>g<bt>r\t%0,%1
    wcdgb\t%v0,%v1,0,0"
   [(set_attr "op_type"      "RRE,VRR")
    (set_attr "type"         "itof<mode>" )
-   (set_attr "cpu_facility" "*,vec")])
+   (set_attr "cpu_facility" "*,vec")
+   (set_attr "disabled"     "0,<nDFDI>")])
 
 ; cxfbr, cdfbr, cefbr
 (define_insn "floatsi<mode>2"
@@ -5462,47 +5457,53 @@
 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
 ; FIXME: wfadb does not clobber cc
 (define_insn "add<mode>3"
-  [(set (match_operand:FP 0 "register_operand"                 "=f,   f,<vf>")
-        (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,   0,<v0>")
-		 (match_operand:FP 2 "general_operand"          "f,<Rf>,<vf>")))
+  [(set (match_operand:FP 0 "register_operand"              "=f,f,f,v")
+        (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
+		 (match_operand:FP 2 "general_operand"       "f,f,R,v")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT"
   "@
-   a<xde><bt>r\t%0,<op1>%2
+   a<xde>tr\t%0,%1,%2
+   a<xde>br\t%0,%2
    a<xde>b\t%0,%2
    wfadb\t%v0,%v1,%v2"
-  [(set_attr "op_type"      "<RRer>,RXE,VRR")
+  [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fsimp<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "disabled"     "<BFP>,<DFP>,<nDSF>,<nDFDI>")])
 
 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
 (define_insn "*add<mode>3_cc"
   [(set (reg CC_REGNUM)
-	(compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
-			  (match_operand:FP 2 "general_operand"      " f,<Rf>"))
+	(compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
+			  (match_operand:FP 2 "general_operand"       "f,f,R"))
 		 (match_operand:FP 3 "const0_operand" "")))
-   (set (match_operand:FP 0 "register_operand" "=f,f")
+   (set (match_operand:FP 0 "register_operand" "=f,f,f")
 	(plus:FP (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
-   a<xde><bt>r\t%0,<op1>%2
+   a<xde>tr\t%0,%1,%2
+   a<xde>br\t%0,%2
    a<xde>b\t%0,%2"
-  [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<mode>")])
+  [(set_attr "op_type"  "RRF,RRE,RXE")
+   (set_attr "type"     "fsimp<mode>")
+   (set_attr "disabled" "<BFP>,<DFP>,<nDSF>")])
 
 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
 (define_insn "*add<mode>3_cconly"
   [(set (reg CC_REGNUM)
-	(compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
-			   (match_operand:FP 2 "general_operand"      " f,<Rf>"))
+	(compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
+			  (match_operand:FP 2 "general_operand"       "f,f,R"))
 		 (match_operand:FP 3 "const0_operand" "")))
-   (clobber (match_scratch:FP 0 "=f,f"))]
+   (clobber (match_scratch:FP 0 "=f,f,f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
-   a<xde><bt>r\t%0,<op1>%2
+   a<xde>tr\t%0,%1,%2
+   a<xde>br\t%0,%2
    a<xde>b\t%0,%2"
-  [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<mode>")])
+  [(set_attr "op_type"  "RRF,RRE,RXE")
+   (set_attr "type"     "fsimp<mode>")
+   (set_attr "disabled" "<BFP>,<DFP>,<nDSF>")])
 
 ;
 ; Pointer add instruction patterns
@@ -5886,47 +5887,53 @@
 
 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
 (define_insn "sub<mode>3"
-  [(set (match_operand:FP           0 "register_operand"   "=f,   f,<vf>")
-        (minus:FP (match_operand:FP 1 "register_operand" "<f0>,   0,<v0>")
-                  (match_operand:FP 2 "general_operand"     "f,<Rf>,<vf>")))
+  [(set (match_operand:FP           0 "register_operand" "=f,f,f,v")
+        (minus:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
+                  (match_operand:FP 2 "general_operand"   "f,f,R,v")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT"
   "@
-   s<xde><bt>r\t%0,<op1>%2
+   s<xde>tr\t%0,%1,%2
+   s<xde>br\t%0,%2
    s<xde>b\t%0,%2
    wfsdb\t%v0,%v1,%v2"
-  [(set_attr "op_type"      "<RRer>,RXE,VRR")
+  [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fsimp<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "disabled"     "<BFP>,<DFP>,<nDSF>,<nDFDI>")])
 
 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
 (define_insn "*sub<mode>3_cc"
   [(set (reg CC_REGNUM)
-	(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
-                           (match_operand:FP 2 "general_operand"      "f,<Rf>"))
+	(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
+                           (match_operand:FP 2 "general_operand"      "f,f,R"))
 		 (match_operand:FP 3 "const0_operand" "")))
-   (set (match_operand:FP 0 "register_operand" "=f,f")
+   (set (match_operand:FP 0 "register_operand" "=f,f,f")
 	(minus:FP (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
-   s<xde><bt>r\t%0,<op1>%2
+   s<xde>tr\t%0,%1,%2
+   s<xde>br\t%0,%2
    s<xde>b\t%0,%2"
-  [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<mode>")])
+  [(set_attr "op_type"  "RRF,RRE,RXE")
+   (set_attr "type"     "fsimp<mode>")
+   (set_attr "disabled" "<BFP>,<DFP>,<nDSF>")])
 
 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
 (define_insn "*sub<mode>3_cconly"
   [(set (reg CC_REGNUM)
-	(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
-			   (match_operand:FP 2 "general_operand"      "f,<Rf>"))
+	(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
+			   (match_operand:FP 2 "general_operand"      "f,f,R"))
 		 (match_operand:FP 3 "const0_operand" "")))
-   (clobber (match_scratch:FP 0 "=f,f"))]
+   (clobber (match_scratch:FP 0 "=f,f,f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
-   s<xde><bt>r\t%0,<op1>%2
+   s<xde>tr\t%0,%1,%2
+   s<xde>br\t%0,%2
    s<xde>b\t%0,%2"
-  [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<mode>")])
+  [(set_attr "op_type"  "RRF,RRE,RXE")
+   (set_attr "type"     "fsimp<mode>")
+   (set_attr "disabled" "<BFP>,<DFP>,<nDSF>")])
 
 
 ;;
@@ -6308,24 +6315,26 @@
 
 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
 (define_insn "mul<mode>3"
-  [(set (match_operand:FP          0 "register_operand"        "=f,   f,<vf>")
-        (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,   0,<v0>")
-                 (match_operand:FP 2 "general_operand"          "f,<Rf>,<vf>")))]
+  [(set (match_operand:FP          0 "register_operand"     "=f,f,f,v")
+        (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
+                 (match_operand:FP 2 "general_operand"       "f,f,R,v")))]
   "TARGET_HARD_FLOAT"
   "@
-   m<xdee><bt>r\t%0,<op1>%2
+   m<xdee>tr\t%0,%1,%2
+   m<xdee>br\t%0,%2
    m<xdee>b\t%0,%2
    wfmdb\t%v0,%v1,%v2"
-  [(set_attr "op_type"      "<RRer>,RXE,VRR")
+  [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fmul<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "disabled"     "<BFP>,<DFP>,<nDSF>,<nDFDI>")])
 
 ; madbr, maebr, maxb, madb, maeb
 (define_insn "fma<mode>4"
-  [(set (match_operand:DSF          0 "register_operand"     "=f,f,<vf>")
-	(fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>")
-		 (match_operand:DSF 2 "nonimmediate_operand"  "f,R,<vf>")
-		 (match_operand:DSF 3 "register_operand"      "0,0,<v0>")))]
+  [(set (match_operand:DSF          0 "register_operand"     "=f,f,v")
+	(fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
+		 (match_operand:DSF 2 "nonimmediate_operand"  "f,R,v")
+		 (match_operand:DSF 3 "register_operand"      "0,0,v")))]
   "TARGET_HARD_FLOAT"
   "@
    ma<xde>br\t%0,%1,%2
@@ -6333,14 +6342,15 @@
    wfmadb\t%v0,%v1,%v2,%v3"
   [(set_attr "op_type"      "RRE,RXE,VRR")
    (set_attr "type"         "fmadd<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,vec")
+   (set_attr "disabled"     "0,0,<nDFDI>")])
 
 ; msxbr, msdbr, msebr, msxb, msdb, mseb
 (define_insn "fms<mode>4"
-  [(set (match_operand:DSF                   0 "register_operand"     "=f,f,<vf>")
-	(fma:DSF (match_operand:DSF          1 "nonimmediate_operand" "%f,f,<vf>")
-		 (match_operand:DSF          2 "nonimmediate_operand"  "f,R,<vf>")
-		 (neg:DSF (match_operand:DSF 3 "register_operand"      "0,0,<v0>"))))]
+  [(set (match_operand:DSF                   0 "register_operand"     "=f,f,v")
+	(fma:DSF (match_operand:DSF          1 "nonimmediate_operand" "%f,f,v")
+		 (match_operand:DSF          2 "nonimmediate_operand"  "f,R,v")
+		 (neg:DSF (match_operand:DSF 3 "register_operand"      "0,0,v"))))]
   "TARGET_HARD_FLOAT"
   "@
    ms<xde>br\t%0,%1,%2
@@ -6348,7 +6358,8 @@
    wfmsdb\t%v0,%v1,%v2,%v3"
   [(set_attr "op_type"      "RRE,RXE,VRR")
    (set_attr "type"         "fmadd<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,vec")
+   (set_attr "disabled"     "0,0,<nDFDI>")])
 
 ;;
 ;;- Divide and modulo instructions.
@@ -6774,17 +6785,19 @@
 
 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
 (define_insn "div<mode>3"
-  [(set (match_operand:FP         0 "register_operand"   "=f,   f,<vf>")
-        (div:FP (match_operand:FP 1 "register_operand" "<f0>,   0,<v0>")
-		(match_operand:FP 2 "general_operand"     "f,<Rf>,<vf>")))]
+  [(set (match_operand:FP         0 "register_operand" "=f,f,f,v")
+        (div:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
+		(match_operand:FP 2 "general_operand"   "f,f,R,v")))]
   "TARGET_HARD_FLOAT"
   "@
-   d<xde><bt>r\t%0,<op1>%2
+   d<xde>tr\t%0,%1,%2
+   d<xde>br\t%0,%2
    d<xde>b\t%0,%2
    wfddb\t%v0,%v1,%v2"
-  [(set_attr "op_type"      "<RRer>,RXE,VRR")
+  [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fdiv<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "disabled"     "<BFP>,<DFP>,<nDSF>,<nDFDI>")])
 
 
 ;;
@@ -7995,8 +8008,8 @@
 ; lcxbr, lcdbr, lcebr
 ; FIXME: wflcdb does not clobber cc
 (define_insn "*neg<mode>2"
-  [(set (match_operand:BFP          0 "register_operand" "=f,<vf>")
-        (neg:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>")))
+  [(set (match_operand:BFP          0 "register_operand" "=f,v")
+        (neg:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT"
   "@
@@ -8004,7 +8017,8 @@
    wflcdb\t%0,%1"
   [(set_attr "op_type"      "RRE,VRR")
    (set_attr "cpu_facility" "*,vec")
-   (set_attr "type"         "fsimp<mode>,*")])
+   (set_attr "type"         "fsimp<mode>,*")
+   (set_attr "disabled"     "0,<nDFDI>")])
 
 
 ;;
@@ -8117,8 +8131,8 @@
 ; lpxbr, lpdbr, lpebr
 ; FIXME: wflpdb does not clobber cc
 (define_insn "*abs<mode>2"
-  [(set (match_operand:BFP          0 "register_operand" "=f,<vf>")
-        (abs:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>")))
+  [(set (match_operand:BFP          0 "register_operand" "=f,v")
+        (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT"
   "@
@@ -8126,7 +8140,8 @@
     wflpdb\t%0,%1"
   [(set_attr "op_type"      "RRE,VRR")
    (set_attr "cpu_facility" "*,vec")
-   (set_attr "type"         "fsimp<mode>,*")])
+   (set_attr "type"         "fsimp<mode>,*")
+   (set_attr "disabled"     "0,<nDFDI>")])
 
 
 ;;
@@ -8232,8 +8247,8 @@
 ; lnxbr, lndbr, lnebr
 ; FIXME: wflndb does not clobber cc
 (define_insn "*negabs<mode>2"
-  [(set (match_operand:BFP                   0 "register_operand" "=f,<vf>")
-        (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>"))))
+  [(set (match_operand:BFP                   0 "register_operand" "=f,v")
+        (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v"))))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT"
   "@
@@ -8241,7 +8256,8 @@
    wflndb\t%0,%1"
   [(set_attr "op_type"      "RRE,VRR")
    (set_attr "cpu_facility" "*,vec")
-   (set_attr "type"         "fsimp<mode>,*")])
+   (set_attr "type"         "fsimp<mode>,*")
+   (set_attr "disabled"     "0,<nDFDI>")])
 
 ;;
 ;;- Square root instructions.
@@ -8253,8 +8269,8 @@
 
 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
 (define_insn "sqrt<mode>2"
-  [(set (match_operand:BFP           0 "register_operand" "=f,   f,<vf>")
-	(sqrt:BFP (match_operand:BFP 1 "general_operand"   "f,<Rf>,<vf>")))]
+  [(set (match_operand:BFP           0 "register_operand" "=f,f,v")
+	(sqrt:BFP (match_operand:BFP 1 "general_operand"   "f,R,v")))]
   "TARGET_HARD_FLOAT"
   "@
    sq<xde>br\t%0,%1
@@ -8262,7 +8278,8 @@
    wfsqdb\t%v0,%v1"
   [(set_attr "op_type"      "RRE,RXE,VRR")
    (set_attr "type"         "fsqrt<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,vec")
+   (set_attr "disabled"     "0,<nDSF>,<nDFDI>")])
 
 
 ;;
