diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index eeaf1ae..e1a2bc6 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -34,6 +34,11 @@
   (and (match_code "const_int, const_double,const_vector")
        (match_test "op == CONSTM1_RTX (mode)")))
 
+;; Return true if OP is a 4 bit mask operand
+(define_predicate "const_mask_operand"
+  (and (match_code "const_int")
+       (match_test "UINTVAL (op) < 16")))
+
 ;; Return true if OP is constant.
 
 (define_special_predicate "consttable_operand"
diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def
index 0b6961e..b0a86e9 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -2470,15 +2470,15 @@ OB_DEF     (s390_vec_ctd,               s390_vec_ctd_s64,   s390_vec_ctd_u64,
 OB_DEF_VAR (s390_vec_ctd_s64,           s390_vec_ctd_s64,   O2_U5,              BT_OV_V2DF_V2DI_INT)                     /* vcdgb */
 OB_DEF_VAR (s390_vec_ctd_u64,           s390_vec_ctd_u64,   O2_U5,              BT_OV_V2DF_UV2DI_INT)                    /* vcdlgb */
 
-B_DEF      (s390_vec_ctd_s64,           vec_ctd_s64,        0,                  B_VX,               O2_U5,              BT_FN_V2DF_V2DI_INT)                     /* vcdgb */
-B_DEF      (s390_vec_ctd_u64,           vec_ctd_u64,        0,                  B_VX,               O2_U5,              BT_FN_V2DF_UV2DI_INT)                    /* vcdlgb */
-B_DEF      (s390_vcdgb,                 vec_di_to_df_s64,   0,                  B_VX,               O2_U5,              BT_FN_V2DF_V2DI_INT)
-B_DEF      (s390_vcdlgb,                vec_di_to_df_u64,   0,                  B_VX,               O2_U5,              BT_FN_V2DF_UV2DI_INT)
-B_DEF      (s390_vec_ctsl,              vec_ctsl,           0,                  B_VX,               O2_U5,              BT_FN_V2DI_V2DF_INT)                     /* vcgdb */
-B_DEF      (s390_vec_ctul,              vec_ctul,           0,                  B_VX,               O2_U5,              BT_FN_UV2DI_V2DF_INT)                    /* vclgdb */
-B_DEF      (s390_vcgdb,                 vec_df_to_di_s64,   0,                  B_VX,               O2_U5,              BT_FN_V2DI_V2DF_INT)
-B_DEF      (s390_vclgdb,                vec_df_to_di_u64,   0,                  B_VX,               O2_U5,              BT_FN_UV2DI_V2DF_INT)
-B_DEF      (s390_vfidb,                 vfidb,              0,                  B_VX,               O2_U4 | O3_U4,      BT_FN_V2DF_V2DF_UCHAR_UCHAR)
+B_DEF      (s390_vec_ctd_s64,           vec_ctd_s64,        0,                  B_VX,               O2_U3,              BT_FN_V2DF_V2DI_INT)                     /* vcdgb */
+B_DEF      (s390_vec_ctd_u64,           vec_ctd_u64,        0,                  B_VX,               O2_U3,              BT_FN_V2DF_UV2DI_INT)                    /* vcdlgb */
+B_DEF      (s390_vcdgb,                 vec_di_to_df_s64,   0,                  B_VX,               O2_U3,              BT_FN_V2DF_V2DI_INT)                     /* vcdgb */
+B_DEF      (s390_vcdlgb,                vec_di_to_df_u64,   0,                  B_VX,               O2_U3,              BT_FN_V2DF_UV2DI_INT)                    /* vcdlgb */
+B_DEF      (s390_vec_ctsl,              vec_ctsl,           0,                  B_VX,               O2_U3,              BT_FN_V2DI_V2DF_INT)                     /* vcgdb */
+B_DEF      (s390_vec_ctul,              vec_ctul,           0,                  B_VX,               O2_U3,              BT_FN_UV2DI_V2DF_INT)                    /* vclgdb */
+B_DEF      (s390_vcgdb,                 vec_df_to_di_s64,   0,                  B_VX,               O2_U3,              BT_FN_V2DI_V2DF_INT)                     /* vcgdb */
+B_DEF      (s390_vclgdb,                vec_df_to_di_u64,   0,                  B_VX,               O2_U3,              BT_FN_UV2DI_V2DF_INT)                    /* vclgdb */
+B_DEF      (s390_vfidb,                 vfidb,              0,                  B_VX,               O2_U4 | O3_U3,      BT_FN_V2DF_V2DF_UCHAR_UCHAR)
 B_DEF      (s390_vec_ld2f,              vec_ld2f,           0,                  B_VX,               0,                  BT_FN_V2DF_FLTCONSTPTR)                  /* vldeb */
 B_DEF      (s390_vec_st2f,              vec_st2f,           0,                  B_VX,               0,                  BT_FN_VOID_V2DF_FLTPTR)                  /* vledb */
 B_DEF      (s390_vfmadb,                fmav2df4,           0,                  B_VX,               0,                  BT_FN_V2DF_V2DF_V2DF_V2DF)
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index d4f652a..c9f5890 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -364,8 +364,8 @@
 	 (vec_select:<non_vec>
 	  (match_operand:V_HW 1 "register_operand"  "v")
 	  (parallel
-	   [(match_operand:QI 2 "immediate_operand" "C")]))))]
-  "TARGET_VX"
+	   [(match_operand:QI 2 "const_mask_operand" "C")]))))]
+  "TARGET_VX && UINTVAL (operands[2]) < GET_MODE_NUNITS (<V_HW:MODE>mode)"
   "vrep<bhfgq>\t%v0,%v1,%2"
   [(set_attr "op_type" "VRI")])
 
@@ -1073,7 +1073,7 @@
   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
 	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
 			   (match_operand:VI_HW_QHS 2 "register_operand" "v")
-			   (match_operand:QI 3 "immediate_operand" "C")]
+			   (match_operand:QI 3 "const_mask_operand" "C")]
 			  UNSPEC_VEC_VFENE))
    (set (reg:CCRAW CC_REGNUM)
 	(unspec:CCRAW [(match_dup 1)
diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index ff7408a..b772439 100644
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -67,20 +67,20 @@
 ; Vector gather element
 
 (define_insn "vec_gather_element<mode>"
-  [(set (match_operand:V_HW_32_64                     0 "register_operand" "=v")
-	(unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand"  "0")
-			    (match_operand:<tointvec> 2 "register_operand"  "v")
-			    (match_operand:BLK        3 "memory_operand"   "QR")
-			    (match_operand:QI         4 "immediate_operand" "C")]
+  [(set (match_operand:V_HW_32_64                     0 "register_operand"  "=v")
+	(unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand"   "0")
+			    (match_operand:<tointvec> 2 "register_operand"   "v")
+			    (match_operand:BLK        3 "memory_operand"    "QR")
+			    (match_operand:QI         4 "const_mask_operand" "C")]
 			   UNSPEC_VEC_GATHER))]
-  "TARGET_VX"
+  "TARGET_VX && UINTVAL (operands[4]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)"
   "vge<bhfgq>\t%0,%O3(%v2,%R3),%b4"
   [(set_attr "op_type" "VRV")])
 
 (define_expand "vec_genmask<mode>"
   [(match_operand:VI_HW 0 "register_operand" "=v")
-   (match_operand:QI    1 "immediate_operand" "C")
-   (match_operand:QI    2 "immediate_operand" "C")]
+   (match_operand:QI    1 "const_int_operand" "C")
+   (match_operand:QI    2 "const_int_operand" "C")]
   "TARGET_VX"
 {
   int nunits = GET_MODE_NUNITS (<VI_HW:MODE>mode);
@@ -120,8 +120,8 @@
 
 (define_expand "vec_genbytemaskv16qi"
   [(match_operand:V16QI 0 "register_operand"  "")
-   (match_operand       1 "immediate_operand" "")]
-  "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'K', \"K\")"
+   (match_operand:HI    1 "const_int_operand" "")]
+  "TARGET_VX"
 {
   int i;
   unsigned mask = 0x8000;
@@ -177,11 +177,11 @@
   [(set_attr "op_type" "VRX")])
 
 (define_insn "vlbb"
-  [(set (match_operand:V16QI              0 "register_operand"  "=v")
-	(unspec:V16QI [(match_operand:BLK 1 "memory_operand"    "QR")
-		       (match_operand:HI  2 "immediate_operand" " K")]
+  [(set (match_operand:V16QI              0 "register_operand"   "=v")
+	(unspec:V16QI [(match_operand:BLK 1 "memory_operand"     "QR")
+		       (match_operand:QI  2 "const_mask_operand"  "C")]
 		      UNSPEC_VEC_LOAD_BNDRY))]
-  "TARGET_VX"
+  "TARGET_VX && UINTVAL (operands[2]) < 7"
   "vlbb\t%v0,%1,%2"
   [(set_attr "op_type" "VRX")])
 
@@ -351,10 +351,10 @@
   [(set_attr "op_type" "VRR")])
 
 (define_expand "vec_permi<mode>"
-  [(set (match_operand:V_HW_64                  0 "register_operand"  "")
-	(unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand"  "")
-			 (match_operand:V_HW_64 2 "register_operand"  "")
-			 (match_operand:QI      3 "immediate_operand" "")]
+  [(set (match_operand:V_HW_64                  0 "register_operand"   "")
+	(unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand"   "")
+			 (match_operand:V_HW_64 2 "register_operand"   "")
+			 (match_operand:QI      3 "const_mask_operand" "")]
 			UNSPEC_VEC_PERMI))]
   "TARGET_VX"
 {
@@ -363,12 +363,12 @@
 })
 
 (define_insn "*vec_permi<mode>"
-  [(set (match_operand:V_HW_64                  0 "register_operand" "=v")
-	(unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand"  "v")
-			 (match_operand:V_HW_64 2 "register_operand"  "v")
-			 (match_operand:QI      3 "immediate_operand" "C")]
+  [(set (match_operand:V_HW_64                  0 "register_operand"  "=v")
+	(unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand"   "v")
+			 (match_operand:V_HW_64 2 "register_operand"   "v")
+			 (match_operand:QI      3 "const_mask_operand" "C")]
 			UNSPEC_VEC_PERMI))]
-  "TARGET_VX"
+  "TARGET_VX && (UINTVAL (operands[3]) & 10) == 0"
   "vpdi\t%v0,%v1,%v2,%b3"
   [(set_attr "op_type" "VRR")])
 
@@ -382,7 +382,7 @@
 	(vec_duplicate:V_HW (vec_select:<non_vec>
 			     (match_operand:V_HW 1 "register_operand"  "")
 			     (parallel
-			      [(match_operand:QI 2 "immediate_operand" "")]))))]
+			      [(match_operand:QI 2 "const_mask_operand" "")]))))]
   "TARGET_VX")
 
 ; Vector scatter element
@@ -393,13 +393,13 @@
 (define_insn "vec_scatter_elementv4si_DI"
   [(set (mem:SI
 	 (plus:DI (zero_extend:DI
-		   (unspec:SI [(match_operand:V4SI 1 "register_operand"  "v")
-			       (match_operand:DI   3 "immediate_operand" "I")]
+		   (unspec:SI [(match_operand:V4SI 1 "register_operand"   "v")
+			       (match_operand:QI   3 "const_mask_operand" "C")]
 			      UNSPEC_VEC_EXTRACT))
-		  (match_operand:SI                2 "address_operand"  "ZQ")))
-	(unspec:SI [(match_operand:V4SI            0 "register_operand"  "v")
+		  (match_operand:SI                2 "address_operand"   "ZQ")))
+	(unspec:SI [(match_operand:V4SI            0 "register_operand"   "v")
 		    (match_dup 3)] UNSPEC_VEC_EXTRACT))]
-  "TARGET_VX && TARGET_64BIT"
+  "TARGET_VX && TARGET_64BIT && UINTVAL (operands[3]) < 4"
   "vscef\t%v0,%O2(%v1,%R2),%3"
   [(set_attr "op_type" "VRV")])
 
@@ -407,13 +407,13 @@
 (define_insn "vec_scatter_element<V_HW_64:mode>_SI"
   [(set (mem:<non_vec>
 	 (plus:SI (subreg:SI
-		   (unspec:<non_vec_int> [(match_operand:V_HW_64 1 "register_operand"  "v")
-					  (match_operand:DI      3 "immediate_operand" "I")]
+		   (unspec:<non_vec_int> [(match_operand:V_HW_64 1 "register_operand"   "v")
+					  (match_operand:QI      3 "const_mask_operand" "C")]
 					 UNSPEC_VEC_EXTRACT) 4)
-		  (match_operand:SI                              2 "address_operand"  "ZQ")))
-	(unspec:<non_vec> [(match_operand:V_HW_64                0 "register_operand"  "v")
+		  (match_operand:SI                              2 "address_operand"   "ZQ")))
+	(unspec:<non_vec> [(match_operand:V_HW_64                0 "register_operand"   "v")
 			   (match_dup 3)] UNSPEC_VEC_EXTRACT))]
-  "TARGET_VX && !TARGET_64BIT"
+  "TARGET_VX && !TARGET_64BIT && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_64:MODE>mode)"
   "vsce<V_HW_64:bhfgq>\t%v0,%O2(%v1,%R2),%3"
   [(set_attr "op_type" "VRV")])
 
@@ -421,13 +421,13 @@
 (define_insn "vec_scatter_element<mode>_<non_vec_int>"
   [(set (mem:<non_vec>
 	 (plus:<non_vec_int> (unspec:<non_vec_int>
-			      [(match_operand:<tointvec> 1 "register_operand"  "v")
-			       (match_operand:DI         3 "immediate_operand" "I")]
+			      [(match_operand:<tointvec> 1 "register_operand"   "v")
+			       (match_operand:QI         3 "const_mask_operand" "C")]
 			      UNSPEC_VEC_EXTRACT)
-			     (match_operand:DI           2 "address_operand"  "ZQ")))
-	(unspec:<non_vec> [(match_operand:V_HW_32_64     0 "register_operand"  "v")
+			     (match_operand:DI           2 "address_operand"   "ZQ")))
+	(unspec:<non_vec> [(match_operand:V_HW_32_64     0 "register_operand"   "v")
 			   (match_dup 3)] UNSPEC_VEC_EXTRACT))]
-  "TARGET_VX"
+  "TARGET_VX && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)"
   "vsce<bhfgq>\t%v0,%O2(%v1,%R2),%3"
   [(set_attr "op_type" "VRV")])
 
@@ -438,7 +438,7 @@
   [(match_operand:V_HW_32_64 0 "register_operand" "")
    (match_operand:<tointvec> 1 "register_operand" "")
    (match_operand 2 "address_operand" "")
-   (match_operand:DI 3 "immediate_operand" "")]
+   (match_operand:QI 3 "const_mask_operand" "")]
   "TARGET_VX"
 {
   if (TARGET_64BIT)
@@ -1042,7 +1042,7 @@
 	(unspec:VI_HW [(match_operand:VI_HW 1 "register_operand"  "0")
 		       (match_operand:VI_HW 2 "register_operand"  "v")
 		       (match_operand:VI_HW 3 "register_operand"  "v")
-		       (match_operand:SI    4 "immediate_operand" "I")]
+		       (match_operand:QI    4 "const_int_operand" "C")]
 		      UNSPEC_VEC_RL_MASK))]
   "TARGET_VX"
   "verim<bhfgq>\t%v0,%v2,%v3,%b4"
@@ -1079,7 +1079,7 @@
   [(set (match_operand:V_HW 0 "register_operand"              "=v")
 	(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
 		      (match_operand:V_HW 2 "register_operand" "v")
-		      (match_operand:DI 3 "immediate_operand" "C")]
+		      (match_operand:QI 3 "const_int_operand"  "C")]
 		     UNSPEC_VEC_SLDB))]
   "TARGET_VX"
   "vsldb\t%v0,%v1,%v2,%b3"
@@ -1089,7 +1089,7 @@
   [(set (match_operand:V_HW 0 "register_operand"               "")
 	(unspec:V_HW [(match_operand:V_HW 1 "register_operand" "")
 		      (match_operand:V_HW 2 "register_operand" "")
-		      (match_operand:DI 3 "immediate_operand"  "")]
+		      (match_operand:QI 3 "const_int_operand"  "")]
 		     UNSPEC_VEC_SLDB))]
   "TARGET_VX"
 {
@@ -1262,7 +1262,7 @@
   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
 	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
 			   (match_operand:VI_HW_QHS 2 "register_operand" "v")
-			   (match_operand:SI        3 "immediate_operand" "C")]
+			   (match_operand:QI        3 "const_mask_operand" "C")]
 			  UNSPEC_VEC_VFAE))]
   "TARGET_VX"
 {
@@ -1282,9 +1282,9 @@
 ; vfaezbs, vfaezhs, vfaezfs
 (define_insn "*vfaes<mode>"
   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
-	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
-			   (match_operand:VI_HW_QHS 2 "register_operand" "v")
-			   (match_operand:SI        3 "immediate_operand" "C")]
+	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"   "v")
+			   (match_operand:VI_HW_QHS 2 "register_operand"   "v")
+			   (match_operand:QI        3 "const_mask_operand" "C")]
 			  UNSPEC_VEC_VFAE))
    (set (reg:CCRAW CC_REGNUM)
 	(unspec:CCRAW [(match_dup 1)
@@ -1307,9 +1307,9 @@
 
 (define_expand "vfaez<mode>"
   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
-	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
-			   (match_operand:VI_HW_QHS 2 "register_operand" "v")
-			   (match_operand:SI        3 "immediate_operand" "C")]
+	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "")
+			   (match_operand:VI_HW_QHS 2 "register_operand"  "")
+			   (match_operand:QI        3 "const_mask_operand" "")]
 			  UNSPEC_VEC_VFAE))]
   "TARGET_VX"
 {
@@ -1319,9 +1319,9 @@
 (define_expand "vfaes<mode>"
   [(parallel
     [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
-	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
-			   (match_operand:VI_HW_QHS 2 "register_operand" "")
-			   (match_operand:SI        3 "immediate_operand" "C")]
+	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "")
+			   (match_operand:VI_HW_QHS 2 "register_operand"  "")
+			   (match_operand:QI        3 "const_mask_operand" "")]
 			  UNSPEC_VEC_VFAE))
    (set (reg:CCRAW CC_REGNUM)
 	(unspec:CCRAW [(match_dup 1)
@@ -1338,9 +1338,9 @@
 (define_expand "vfaezs<mode>"
   [(parallel
     [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
-	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
-			   (match_operand:VI_HW_QHS 2 "register_operand" "")
-			   (match_operand:SI        3 "immediate_operand" "C")]
+	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "")
+			   (match_operand:VI_HW_QHS 2 "register_operand"  "")
+			   (match_operand:SI        3 "const_mask_operand" "")]
 			  UNSPEC_VEC_VFAE))
    (set (reg:CCRAW CC_REGNUM)
 	(unspec:CCRAW [(match_dup 1)
@@ -1363,7 +1363,7 @@
   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
 	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
 			   (match_operand:VI_HW_QHS 2 "register_operand" "v")
-			   (match_operand:QI 3 "immediate_operand" "C")]
+			   (match_operand:QI 3 "const_mask_operand" "C")]
 			  UNSPEC_VEC_VFEE))
    (set (reg:CCRAW CC_REGNUM)
 	(unspec:CCRAW [(match_dup 1)
@@ -1541,11 +1541,11 @@
 ; vstrcb, vstrch, vstrcf
 ; vstrczb, vstrczh, vstrczf
 (define_insn "vstrc<mode>"
-  [(set (match_operand:VI_HW_QHS                    0 "register_operand" "=v")
-	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "v")
-			   (match_operand:VI_HW_QHS 2 "register_operand"  "v")
-			   (match_operand:VI_HW_QHS 3 "register_operand"  "v")
-			   (match_operand:SI        4 "immediate_operand" "C")]
+  [(set (match_operand:VI_HW_QHS                    0 "register_operand"  "=v")
+	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"   "v")
+			   (match_operand:VI_HW_QHS 2 "register_operand"   "v")
+			   (match_operand:VI_HW_QHS 3 "register_operand"   "v")
+			   (match_operand:QI        4 "const_mask_operand" "C")]
 			  UNSPEC_VEC_VSTRC))]
   "TARGET_VX"
 {
@@ -1564,11 +1564,11 @@
 ; vstrcbs, vstrchs, vstrcfs
 ; vstrczbs, vstrczhs, vstrczfs
 (define_insn "*vstrcs<mode>"
-  [(set (match_operand:VI_HW_QHS                    0 "register_operand" "=v")
-	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "v")
-			   (match_operand:VI_HW_QHS 2 "register_operand"  "v")
-			   (match_operand:VI_HW_QHS 3 "register_operand"  "v")
-			   (match_operand:SI        4 "immediate_operand" "C")]
+  [(set (match_operand:VI_HW_QHS                    0 "register_operand"  "=v")
+	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"   "v")
+			   (match_operand:VI_HW_QHS 2 "register_operand"   "v")
+			   (match_operand:VI_HW_QHS 3 "register_operand"   "v")
+			   (match_operand:QI        4 "const_mask_operand" "C")]
 			  UNSPEC_VEC_VSTRC))
    (set (reg:CCRAW CC_REGNUM)
 	(unspec:CCRAW [(match_dup 1)
@@ -1591,11 +1591,11 @@
   [(set_attr "op_type" "VRR")])
 
 (define_expand "vstrcz<mode>"
-  [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
-	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
-			   (match_operand:VI_HW_QHS 2 "register_operand" "v")
-			   (match_operand:VI_HW_QHS 3 "register_operand" "v")
-			   (match_operand:SI        4 "immediate_operand" "C")]
+  [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
+	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"   "")
+			   (match_operand:VI_HW_QHS 2 "register_operand"   "")
+			   (match_operand:VI_HW_QHS 3 "register_operand"   "")
+			   (match_operand:QI        4 "const_mask_operand" "")]
 			  UNSPEC_VEC_VSTRC))]
   "TARGET_VX"
 {
@@ -1608,7 +1608,7 @@
 	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
 			   (match_operand:VI_HW_QHS 2 "register_operand" "")
 			   (match_operand:VI_HW_QHS 3 "register_operand" "")
-			   (match_operand:SI        4 "immediate_operand" "C")]
+			   (match_operand:QI        4 "const_mask_operand" "")]
 			  UNSPEC_VEC_VSTRC))
    (set (reg:CCRAW CC_REGNUM)
 	(unspec:CCRAW [(match_dup 1)
@@ -1629,7 +1629,7 @@
 	(unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
 			   (match_operand:VI_HW_QHS 2 "register_operand" "")
 			   (match_operand:VI_HW_QHS 3 "register_operand" "")
-			   (match_operand:SI        4 "immediate_operand" "C")]
+			   (match_operand:QI        4 "const_mask_operand" "")]
 			  UNSPEC_VEC_VSTRC))
    (set (reg:CCRAW CC_REGNUM)
 	(unspec:CCRAW [(match_dup 1)
@@ -1647,11 +1647,11 @@
 
 ; Signed V2DI -> V2DF conversion - inexact exception disabled
 (define_insn "vec_di_to_df_s64"
-  [(set (match_operand:V2DF 0 "register_operand"               "=v")
-	(unspec:V2DF [(match_operand:V2DI 1 "register_operand"  "v")
-		      (match_operand:QI   2 "immediate_operand" "C")]
+  [(set (match_operand:V2DF 0 "register_operand"                "=v")
+	(unspec:V2DF [(match_operand:V2DI 1 "register_operand"   "v")
+		      (match_operand:QI   2 "const_mask_operand" "C")]
 		     UNSPEC_VEC_VCDGB))]
-  "TARGET_VX"
+  "TARGET_VX && UINTVAL (operands[2]) != 2 && UINTVAL (operands[2]) <= 7"
   "vcdgb\t%v0,%v1,4,%b2"
   [(set_attr "op_type" "VRR")])
 
@@ -1661,7 +1661,7 @@
 	(unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
 		      (const_int 0)] ; According to current BFP rounding mode
 		     UNSPEC_VEC_VCDGB))
-   (use (match_operand:QI 2 "immediate_operand" ""))
+   (use (match_operand:QI 2 "const_int_operand" ""))
    (set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
   "TARGET_VX"
 {
@@ -1679,7 +1679,7 @@
 (define_insn "vec_di_to_df_u64"
   [(set (match_operand:V2DF 0 "register_operand"               "=v")
 	(unspec:V2DF [(match_operand:V2DI 1 "register_operand"  "v")
-		      (match_operand:QI   2 "immediate_operand" "C")]
+		      (match_operand:QI   2 "const_int_operand" "C")]
 		     UNSPEC_VEC_VCDLGB))]
   "TARGET_VX"
   "vcdlgb\t%v0,%v1,4,%b2"
@@ -1691,7 +1691,7 @@
 	(unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
 		      (const_int 0)] ; According to current BFP rounding mode
 		     UNSPEC_VEC_VCDLGB))
-   (use (match_operand:QI 2 "immediate_operand" ""))
+   (use (match_operand:QI 2 "const_int_operand" ""))
    (set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
   "TARGET_VX"
 {
@@ -1710,7 +1710,7 @@
 (define_insn "vec_df_to_di_s64"
   [(set (match_operand:V2DI 0 "register_operand"               "=v")
 	(unspec:V2DI [(match_operand:V2DF 1 "register_operand"  "v")
-		      (match_operand:QI   2 "immediate_operand" "C")]
+		      (match_operand:QI   2 "const_int_operand" "C")]
 		     UNSPEC_VEC_VCGDB))]
   "TARGET_VX"
   "vcgdb\t%v0,%v1,4,%b2"
@@ -1718,7 +1718,7 @@
 
 ; The input needs to be multiplied with 2**op2
 (define_expand "vec_ctsl"
-  [(use (match_operand:QI 2 "immediate_operand" ""))
+  [(use (match_operand:QI 2 "const_int_operand" ""))
    (set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
 				 (match_dup 3)))
    (set (match_operand:V2DI 0 "register_operand" "")
@@ -1741,15 +1741,15 @@
 (define_insn "vec_df_to_di_u64"
   [(set (match_operand:V2DI 0 "register_operand"               "=v")
 	(unspec:V2DI [(match_operand:V2DF 1 "register_operand"  "v")
-		      (match_operand:QI   2 "immediate_operand" "C")]
+		      (match_operand:QI   2 "const_mask_operand" "C")]
 		     UNSPEC_VEC_VCLGDB))]
-  "TARGET_VX"
+  "TARGET_VX && UINTVAL (operands[2]) <= 7"
   "vclgdb\t%v0,%v1,4,%b2"
   [(set_attr "op_type" "VRR")])
 
 ; The input needs to be multiplied with 2**op2
 (define_expand "vec_ctul"
-  [(use (match_operand:QI 2 "immediate_operand" ""))
+  [(use (match_operand:QI 2 "const_int_operand" ""))
    (set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
 				 (match_dup 3)))
    (set (match_operand:V2DI 0 "register_operand" "")
@@ -1770,12 +1770,12 @@
 
 ; Vector load fp integer - IEEE inexact exception is suppressed
 (define_insn "vfidb"
-  [(set (match_operand:V2DI               0 "register_operand" "=v")
-	(unspec:V2DI [(match_operand:V2DF 1 "register_operand"  "v")
-		      (match_operand:QI   2 "immediate_operand" "C")
-		      (match_operand:QI   3 "immediate_operand" "C")]
+  [(set (match_operand:V2DI               0 "register_operand"  "=v")
+	(unspec:V2DI [(match_operand:V2DF 1 "register_operand"   "v")
+		      (match_operand:QI   2 "const_mask_operand" "C")
+		      (match_operand:QI   3 "const_mask_operand" "C")]
 		     UNSPEC_VEC_VFIDB))]
-  "TARGET_VX"
+  "TARGET_VX && !(UINTVAL (operands[2]) & 3) && UINTVAL (operands[3]) <= 7"
   "vfidb\t%v0,%v1,%b2,%b3"
   [(set_attr "op_type" "VRR")])
 
@@ -1887,21 +1887,21 @@
 (define_insn "*vftcidb"
   [(set (match_operand:V2DF 0 "register_operand"  "=v")
 	(unspec:V2DF [(match_operand:V2DF 1 "register_operand"  "v")
-		      (match_operand:SI   2 "immediate_operand" "J")]
+		      (match_operand:HI   2 "const_int_operand" "J")]
 		     UNSPEC_VEC_VFTCIDB))
    (set (reg:CCRAW CC_REGNUM)
 	(unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCIDBCC))]
-  "TARGET_VX"
+  "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
   "vftcidb\t%v0,%v1,%x2"
   [(set_attr "op_type" "VRR")])
 
 (define_insn "*vftcidb_cconly"
   [(set (reg:CCRAW CC_REGNUM)
 	(unspec:CCRAW [(match_operand:V2DF 1 "register_operand"  "v")
-		       (match_operand:SI   2 "immediate_operand" "J")]
+		       (match_operand:HI   2 "const_int_operand" "J")]
 		      UNSPEC_VEC_VFTCIDBCC))
    (clobber (match_scratch:V2DI 0 "=v"))]
-  "TARGET_VX"
+  "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
   "vftcidb\t%v0,%v1,%x2"
   [(set_attr "op_type" "VRR")])
 
@@ -1909,13 +1909,13 @@
   [(parallel
     [(set (match_operand:V2DF               0 "register_operand"  "")
 	  (unspec:V2DF [(match_operand:V2DF 1 "register_operand"  "")
-			(match_operand:SI   2 "immediate_operand" "")]
+			(match_operand:HI   2 "const_int_operand" "")]
 		       UNSPEC_VEC_VFTCIDB))
      (set (reg:CCRAW CC_REGNUM)
 	  (unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCIDBCC))])
    (set (match_operand:SI 3 "memory_operand" "")
 	(unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
-  "TARGET_VX")
+  "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")")
 
 ;;
 ;; Integer compares
