From patchwork Mon Oct 26 16:26:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 536104 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E69D61412FD for ; Tue, 27 Oct 2015 03:26:43 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=GhDltLzJ; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding; q=dns; s=default; b=iSibKNuBN2pDg6jJ g6dbSwrpPcTqyHEiwOLbON+qg0aBB2YlGC14Zw/5/uXwF/3+OvDEIDHddKlBuJCL fuHlCFMbaLz46QfCPmFFJl9TbpCxGcLbagxMyY8aJhDjrHAsUomfcWrq6iEYvCBq N8RXzV9SICL4UUjWJMcRWDnOOdE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding; s=default; bh=/HmH19MG7dJto9y5efreyF 4gKjE=; b=GhDltLzJwNwo9KqwyJrVfPNeqirFuOYyoeiwWrxAWN2CpWZR+KoiPX q1xwiB9IywOBKoQQr9wMSr2cqblLsa2zQGnww/r6TIsZWRPEwaMTTT5amCmCAsf5 bMRLji/m37xUYdbjZpn8KUtboNKw5cKX2MlfTbMbTvqYbN5Xv9S/o= Received: (qmail 126843 invoked by alias); 26 Oct 2015 16:26:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 126818 invoked by uid 89); 26 Oct 2015 16:26:34 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 26 Oct 2015 16:26:33 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-29-FOP7Ms_DRSqnUTLbvcBeTA-1; Mon, 26 Oct 2015 16:26:28 +0000 Received: from arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 26 Oct 2015 16:26:28 +0000 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [PATCH][AArch64] Fix ICE on (const_double:HF 0.0) Date: Mon, 26 Oct 2015 16:26:17 +0000 Message-Id: <1445876777-31607-1-git-send-email-alan.lawrence@arm.com> X-MC-Unique: FOP7Ms_DRSqnUTLbvcBeTA-1 X-IsSubscribed: yes The included testcase demonstrates the ICE: aarch64_valid_floating_const (via aarch64_float_const_representable_p) disables HFmode immediates, but allows 0.0. However, *movhf_aarch64 does not allow this insn: (insn 7 6 10 2 (set (mem:HF (reg/f:DI 73) [0 *f_2(D)+0 S2 A16]) (const_double:HF 0.0 [0x0.0p+0])) test.c:8 -1 (nil)) Fix is to allow the second operand to be zero, in the same way as *movsf_aarch64. Bootstrapped + check-gcc on aarch64-none-linux-gnu. New test also passing on arm-none-eabi. OK for trunk? gcc/ChangeLog: * config/aarch64/aarch64.md (*movhf_aarch64): Use aarch64_reg_or_fp_zero for second operand. gcc/testsuite/ChangeLog: * gcc.target/aarch64/fp16/set_zero_1.c: New. --- gcc/config/aarch64/aarch64.md | 2 +- gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 78b9ae2..8895a4e 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1120,7 +1120,7 @@ [(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r") (match_operand:HF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], HFmode) - || register_operand (operands[1], HFmode))" + || aarch64_reg_or_fp_zero (operands[1], HFmode))" "@ mov\\t%0.h[0], %w1 umov\\t%w0, %1.h[0] diff --git a/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c b/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c new file mode 100644 index 0000000..36cadfd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fp16/set_zero_1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-mfp16-format=ieee" { target "arm*-*-*" } } */ + +extern void abort (void); + +__attribute__ ((noinline)) +void +setfoo (__fp16 *f) +{ + *f = 0.0; +} + +int +main (int argc, char **argv) +{ + __fp16 a = 1.0; + setfoo (&a); + if (a != 0.0) + abort (); + return 0; +}