Index: gcc/testsuite/gcc.target/sh/20080410-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/20080410-1.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/20080410-1.c	(working copy)
@@ -1,6 +1,5 @@
-/* { dg-do compile }  */
+/* { dg-do compile { target { little_endian } } }  */
 /* { dg-options "-O0" } */
-/* { dg-skip-if "" { "sh*-*-*" } "-mb" "" }  */
 /* { dg-final { scan-assembler-not "add\tr0,r0" } } */
 
 /* This test checks chain reloads conflicts.  If they don't
Index: gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c
===================================================================
--- gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c	(working copy)
@@ -3,8 +3,7 @@
    (On SH3* and SH4* r0..r7 are banked)
    Call-saved registers r8..r13 also don't need to be restored.
    To test that we look for register push insns such as 'mov.l r0,@-r15'.  */
-/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1*" "-m2*" "-m5*" } { "" } }  */
+/* { dg-do compile { target { { banked_r0r7_isr } && nonpic } } }  */
 /* { dg-options "-O" }  */
 /* { dg-final { scan-assembler-times "rte" 1 } }  */
 /* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } }  */
Index: gcc/testsuite/gcc.target/sh/attr-isr.c
===================================================================
--- gcc/testsuite/gcc.target/sh/attr-isr.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/attr-isr.c	(working copy)
@@ -1,8 +1,7 @@
 /* The call will clobber r0..r7, which will need not be saved/restored, but
    not the call-saved registers r8..r14.  Check this by counting the register
    push insns.  */
-/* { dg-do compile { target { { { sh-*-* sh[1234ble]*-*-* } && { ! sh2a*-*-* } } && nonpic } } } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m2a*" } { "" } } */
+/* { dg-do compile { target { { ! sh2a } && nonpic } } } */
 /* { dg-options "-O" } */
 /* { dg-final { scan-assembler-times "rte" 1} } */
 /* { dg-final { scan-assembler-times "mov.l\tr\[0-7\],@-r15" 8 } }  */
Index: gcc/testsuite/gcc.target/sh/fpul-usage-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/fpul-usage-1.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/fpul-usage-1.c	(working copy)
@@ -1,8 +1,7 @@
 /* Check that the FPUL register is used when reading a float as an int and
    vice versa, as opposed to pushing and popping the values over the stack.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler "fpul" } } */
 /* { dg-final { scan-assembler-not "r15" } } */
 
Index: gcc/testsuite/gcc.target/sh/hiconst.c
===================================================================
--- gcc/testsuite/gcc.target/sh/hiconst.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/hiconst.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile } */
 /* { dg-options "-O1" } */
 
 char a;
Index: gcc/testsuite/gcc.target/sh/mfmovd.c
===================================================================
--- gcc/testsuite/gcc.target/sh/mfmovd.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/mfmovd.c	(working copy)
@@ -1,9 +1,7 @@
 /* Verify that we generate fmov.d instructions to move doubles when -mfmovd 
    option is enabled.  */
-/* { dg-do compile }  */
-/* { dg-require-effective-target hard_float } */
+/* { dg-do compile { target { double_fpu } } }  */
 /* { dg-options "-mfmovd" } */
-/* { dg-skip-if "" { *-*-* }  { "*-single-only" } { "" } } */
 /* { dg-final { scan-assembler "fmov.d" } } */
 
 extern double g;
Index: gcc/testsuite/gcc.target/sh/pr21255-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr21255-3.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr21255-3.c	(working copy)
@@ -1,6 +1,5 @@
-/* { dg-do compile }  */
+/* { dg-do compile { target { double_fpu } } }  */
 /* { dg-options "-O2 -fomit-frame-pointer" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m2e" "-m3e" "*single-only" } { "" } }  */
 /* { dg-final { scan-assembler "mov #?0,r.*; mov #?20,r" } } */
 /* { dg-final { scan-assembler "mov #?1077149696,r.*; mov #?0,r" } } */
 double
Index: gcc/testsuite/gcc.target/sh/pr33135-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr33135-1.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr33135-1.c	(working copy)
@@ -1,8 +1,7 @@
 /* Check that fcmp/eq and fcmp/gt instructions are generated by default
    (implicit -mieee).  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fcmp/eq" 4 } } */
 /* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */
 
@@ -29,4 +28,3 @@
 {
   return a >= b;
 }
-
Index: gcc/testsuite/gcc.target/sh/pr33135-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr33135-2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr33135-2.c	(working copy)
@@ -1,8 +1,7 @@
 /* Check that only the fcmp/gt instruction is generated when specifying
    -ffinite-math-only (implicit -mno-ieee).  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O1 -ffinite-math-only" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-not "fcmp/eq" } } */
 /* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */
 
Index: gcc/testsuite/gcc.target/sh/pr33135-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr33135-3.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr33135-3.c	(working copy)
@@ -1,8 +1,7 @@
 /* Check that fcmp/eq and fcmp/gt instructions are generated when specifying
    -ffinite-math-only and -mieee.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O1 -ffinite-math-only -mieee" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fcmp/eq" 4 } } */
 /* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */
 
@@ -29,4 +28,3 @@
 {
   return a >= b;
 }
-
Index: gcc/testsuite/gcc.target/sh/pr33135-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr33135-4.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr33135-4.c	(working copy)
@@ -1,8 +1,7 @@
 /* Check that only the fcmp/gt instruction is generated when specifying
    -fno-finite-math-only and -mno-ieee.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O1 -fno-finite-math-only -mno-ieee" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-not "fcmp/eq" } } */
 /* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */
 
@@ -29,4 +28,3 @@
 {
   return a >= b;
 }
-
Index: gcc/testsuite/gcc.target/sh/pr39423-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr39423-2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr39423-2.c	(working copy)
@@ -1,9 +1,8 @@
 /* Check that displacement addressing is used for indexed addresses with a
    small offset, instead of re-calculating the index and that the movu.w
    instruction is used on SH2A.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-not "add\t#1" } } */
 /* { dg-final { scan-assembler "movu.w" } } */
 
Index: gcc/testsuite/gcc.target/sh/pr49880-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49880-4.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr49880-4.c	(working copy)
@@ -1,9 +1,8 @@
 /* Check that the option -mdiv=call-fp does not produce calls to the
    library function that uses FPU to implement integer division if FPU insns
    are not supported or are disabled.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { no_fpu } } }  */
 /* { dg-options "-mdiv=call-fp" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" } }  */
 /* { dg-final { scan-assembler-not "sdivsi3_i4\n|udivsi3_i4\n" } }  */
 
 int
Index: gcc/testsuite/gcc.target/sh/pr49880-5.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49880-5.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr49880-5.c	(working copy)
@@ -1,8 +1,7 @@
 /* Check that the option -mdiv=call-fp results in the corresponding library
    function calls on targets that have a double precision FPU.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { double_fpu || use_single_only_fpu } } }  */
 /* { dg-options "-mdiv=call-fp" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m2a" "-m4" "-m4a" "*single-only" } }  */
 /* { dg-final { scan-assembler "sdivsi3_i4\n" } }  */
 /* { dg-final { scan-assembler "udivsi3_i4\n" } }  */
 
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c	(working copy)
@@ -1,7 +1,6 @@
 /* PR target/50749: Verify that post-increment addressing is generated.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 1 } } */
 
 float*
@@ -12,4 +11,3 @@
   *x = r;
   return p;
 }
-
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c	(working copy)
@@ -1,8 +1,7 @@
 /* PR target/50749: Verify that subsequent post-increment addressings
    are generated.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 5 { xfail *-*-*} } } */
 
 float*
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c	(working copy)
@@ -1,8 +1,7 @@
 /* PR target/50749: Verify that post-increment addressing is generated
    inside a loop.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 1 } } */
 
 float
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c	(working copy)
@@ -1,8 +1,7 @@
 /* PR target/50749: Verify that post-increment addressing is generated
    inside a loop.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 3 { xfail *-*-*} } } */
 
 float
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c	(working copy)
@@ -1,7 +1,6 @@
 /* PR target/50749: Verify that pre-decrement addressing is generated.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 1 } } */
 
 float*
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c	(working copy)
@@ -1,8 +1,7 @@
 /* PR target/50749: Verify that subsequent pre-decrement addressings
    are generated.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 5 { xfail *-*-*} } } */
 
 float*
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c	(working copy)
@@ -1,8 +1,7 @@
 /* PR target/50749: Verify that pre-decrement addressing is generated
    inside a loop.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 1 } } */
 
 float*
Index: gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c	(working copy)
@@ -1,8 +1,7 @@
 /* PR target/50749: Verify that pre-decrement addressing is generated
    inside a loop.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 3 { xfail *-*-*} } } */
 
 float*
Index: gcc/testsuite/gcc.target/sh/pr50751-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50751-2.c	(working copy)
@@ -2,9 +2,8 @@
    base address is adjusted only once.  On SH2A this test is skipped because
    there is a 4 byte mov.b insn that can handle larger displacements.  Thus
    on SH2A the base address will not be adjusted in this case.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { ! sh2a } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
 /* { dg-final { scan-assembler-times "add" 2 } } */
 
 void
Index: gcc/testsuite/gcc.target/sh/pr50751-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-3.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50751-3.c	(working copy)
@@ -1,9 +1,8 @@
 /* Check that on SH2A the 4 byte mov.b displacement insn is generated to
    handle larger displacements.  If it is generated correctly, there should
    be no base address adjustments outside the mov.b insns.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-not "add|sub" } } */
 
 void
Index: gcc/testsuite/gcc.target/sh/pr50751-5.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-5.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50751-5.c	(working copy)
@@ -2,9 +2,8 @@
    base address is adjusted only once.  On SH2A this test is skipped because
    there is a 4 byte mov.w insn that can handle larger displacements.  Thus
    on SH2A the base address will not be adjusted in this case.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { ! sh2a } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
 /* { dg-final { scan-assembler-times "add" 2 } } */
 
 void
Index: gcc/testsuite/gcc.target/sh/pr50751-6.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-6.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50751-6.c	(working copy)
@@ -1,9 +1,8 @@
 /* Check that on SH2A the 4 byte mov.w displacement insn is generated to
    handle larger displacements.  If it is generated correctly, there should
    be no base address adjustments outside the mov.w insns.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-not "add|sub" } } */
 
 void
Index: gcc/testsuite/gcc.target/sh/pr50751-8.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr50751-8.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr50751-8.c	(working copy)
@@ -1,9 +1,8 @@
 /* Check that on SH2A the 4 byte movu.b and movu.w displacement insns are
    generated.  This has to be checked with -O2 because some of the patterns
    rely on peepholes.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "movu.b" 4 } } */
 /* { dg-final { scan-assembler-times "movu.w" 3 } } */
 
Index: gcc/testsuite/gcc.target/sh/pr51244-15.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-15.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr51244-15.c	(working copy)
@@ -1,14 +1,17 @@
 /* Check that the redundant test removal code in the *cbranch_t split works
-   as expected on non-SH2A targets.  Because on SH2A the movrt instruction
-   is used, this test is re-used and checked differently in pr51244-16.c.  */
+   as expected.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
+
+/* { dg-final { scan-assembler-not "extu|exts|negc" } } */
 /* { dg-final { scan-assembler-times "tst" 6 } } */
-/* { dg-final { scan-assembler-times "movt" 6 } } */
-/* { dg-final { scan-assembler-times "xor" 3 } } */
-/* { dg-final { scan-assembler-not "extu|exts|negc" } } */
 
+/* { dg-final { scan-assembler-times "movt" 6 { target { ! sh2a } } } } */
+/* { dg-final { scan-assembler-times "xor" 3 { target { ! sh2a } } } } */
+
+/* { dg-final { scan-assembler-times "movt" 3 { target { sh2a } } } } */
+/* { dg-final { scan-assembler-times "movrt" 3 { target { sh2a } } } } */
+
 typedef char bool;
 
 int
Index: gcc/testsuite/gcc.target/sh/pr51244-16.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-16.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr51244-16.c	(working copy)
@@ -1,11 +0,0 @@
-/* Check that the redundant test removal code in the *cbranch_t split works
-   as expected on SH2A targets.  */
-/* { dg-do compile }  */
-/* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
-/* { dg-final { scan-assembler-times "tst" 6 } } */
-/* { dg-final { scan-assembler-times "movt" 3 } } */
-/* { dg-final { scan-assembler-times "movrt" 3 } } */
-/* { dg-final { scan-assembler-not "extu|exts|negc" } } */
-
-#include "pr51244-15.c"
Index: gcc/testsuite/gcc.target/sh/pr51244-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr51244-2.c	(working copy)
@@ -1,12 +1,12 @@
 /* Check that when taking the complement of the T bit using the negc
-   instruction pattern, the constant -1 is loaded only once.
-   On SH2A this test is skipped because the movrt instruction is used
-   to get the complement of the T bit.  */
+   instruction pattern, the constant -1 is loaded only once on non-SH2A and
+   that the movrt insn is generated on SH2A.
 /* { dg-do compile }  */
 /* { dg-options "-O1 -mbranch-cost=2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
-/* { dg-final { scan-assembler-times "mov\t#-1" 1 } } */
 
+/* { dg-final { scan-assembler-times "mov\t#-1" 1 { target { ! sh2a } } } } */
+/* { dg-final { scan-assembler-times "movrt" 4 { target { sh2a } } } } */
+
 void
 testfunc_00 (int* a, int* b, int c, int d)
 {
Index: gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c	(working copy)
@@ -1,14 +0,0 @@
-/* Check that the SH specific sh_treg_combine RTL optimization pass works as
-   expected.  */
-/* { dg-do compile }  */
-/* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
-/* { dg-final { scan-assembler-times "tst" 6 } } */
-/* { dg-final { scan-assembler-not "movt" } } */
-/* { dg-final { scan-assembler-times "nott" 2 } } */
-/* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
-/* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
-/* { dg-final { scan-assembler-times "cmp/gt" 2 } } */
-/* { dg-final { scan-assembler-not "not\t" } } */
-
-#include "pr51244-20.c"
Index: gcc/testsuite/gcc.target/sh/pr51244-20.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-20.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr51244-20.c	(working copy)
@@ -1,17 +1,21 @@
 /* Check that the SH specific sh_treg_combine RTL optimization pass works as
-   expected.  On SH2A the expected insns are slightly different, see
-   pr51244-20-sh2a.c.  */
+   expected.  */
 /* { dg-do compile }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
-/* { dg-final { scan-assembler-times "tst" 7 } } */
-/* { dg-final { scan-assembler-times "movt" 2 } } */
+
+/* { dg-final { scan-assembler-not "not\t" } } */
 /* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
 /* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
 /* { dg-final { scan-assembler-times "cmp/gt" 2 } } */
-/* { dg-final { scan-assembler-not "not\t" } } */
 
+/* { dg-final { scan-assembler-times "tst" 7 { target { ! sh2a } } } } */
+/* { dg-final { scan-assembler-times "movt" 2 { target { ! sh2a } } } } */
 
+/* { dg-final { scan-assembler-times "tst" 6 { target { sh2a } } } } */
+/* { dg-final { scan-assembler-not "movt" { target { sh2a } } } } */
+/* { dg-final { scan-assembler-times "nott" 2 { target { sh2a } } } } */
+
+
 /* non-SH2A: 2x tst, 1x movt, 2x cmp/eq, 1x cmp/hi
    SH2A: 1x tst, 1x nott, 2x cmp/eq, 1x cmp/hi  */
 static inline int
Index: gcc/testsuite/gcc.target/sh/pr51244-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-3.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr51244-3.c	(working copy)
@@ -1,16 +0,0 @@
-/* Check that when taking the complement of the T bit on SH2A, 
-   the movrt instruction is being generated.  */
-/* { dg-do compile }  */
-/* { dg-options "-O1 -mbranch-cost=2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
-/* { dg-final { scan-assembler-times "movrt" 4 } } */
-
-void
-testfunc_00 (int* a, int* b, int c, int d)
-{
-  b[0] = a[0] != c;
-  b[1] = a[1] != d;
-  b[2] = a[2] != c;
-  b[3] = a[3] != d;
-}
-
Index: gcc/testsuite/gcc.target/sh/pr51244-6.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr51244-6.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr51244-6.c	(working copy)
@@ -1,8 +1,7 @@
 /* Check that no unnecessary sign or zero extension insn is generated after
    a negc or movrt insn that stores the inverted T bit in a reg.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-not "extu|exts" } } */
 
 float
Index: gcc/testsuite/gcc.target/sh/pr52483-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr52483-4.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr52483-4.c	(working copy)
@@ -1,8 +1,7 @@
 /* Check that loads/stores from/to volatile floating point mems utilize
    indexed addressing modes. */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "@\\(r0," 2 } } */
 
 float
Index: gcc/testsuite/gcc.target/sh/pr53511-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53511-1.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr53511-1.c	(working copy)
@@ -1,7 +1,6 @@
 /* Verify that the fmac insn is used for the standard fmaf function.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler "fmac" } } */
 
 #include <math.h>
Index: gcc/testsuite/gcc.target/sh/pr53512-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53512-1.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr53512-1.c	(working copy)
@@ -1,8 +1,7 @@
 /* Verify that the fsca insn is used when specifying -mfsca and
   -funsafe-math-optimizations.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { has_fsca } } }  */
 /* { dg-options "-O1 -mfsca -funsafe-math-optimizations" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fsca" 3 } } */
 
 #include <math.h>
Index: gcc/testsuite/gcc.target/sh/pr53512-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53512-2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr53512-2.c	(working copy)
@@ -1,8 +1,7 @@
 /* Verify that the fsca insn is not used when specifying -mno-fsca and
   -funsafe-math-optimizations.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { has_fsca } } }  */
 /* { dg-options "-O1 -mno-fsca -funsafe-math-optimizations" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-not "fsca" } } */
 
 #include <math.h>
Index: gcc/testsuite/gcc.target/sh/pr53512-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53512-3.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr53512-3.c	(working copy)
@@ -1,8 +1,7 @@
 /* Verify that the fsrra insn is used when specifying -mfsrra and
   -funsafe-math-optimizations and -ffinite-math-only.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { has_fsrra } } }  */
 /* { dg-options "-O1 -mfsrra -funsafe-math-optimizations -ffinite-math-only" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler "fsrra" } } */
 
 #include <math.h>
Index: gcc/testsuite/gcc.target/sh/pr53512-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53512-4.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr53512-4.c	(working copy)
@@ -1,8 +1,7 @@
 /* Verify that the fsrra insn is not used when specifying -mno-fsrra and
   -funsafe-math-optimizations and -ffinite-math-only.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { has_fsrra } } }  */
 /* { dg-options "-O1 -mno-fsrra -funsafe-math-optimizations -ffinite-math-only" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-not "fsrra" } } */
 
 #include <math.h>
@@ -12,4 +11,3 @@
 {
   return 1 / sqrtf (x);
 }
-
Index: gcc/testsuite/gcc.target/sh/pr53513-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr53513-1.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr53513-1.c	(working copy)
@@ -1,6 +1,6 @@
 /* Check that fpchg is used to switch FPSCR.PR mode on SH4A.  */
+/* { dg-do compile { target { has_fpchg } } }  */
 /* { dg-additional-options "-O" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" } }  */
 /* { dg-final { scan-assembler "fpchg" } }  */
 /* { dg-final { scan-assembler-not "fpscr" } }  */
 
Index: gcc/testsuite/gcc.target/sh/pr54089-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr54089-2.c	(working copy)
@@ -9,9 +9,8 @@
 	mov	r4,r0
 	rts
 	rotcr	r0  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { has_dyn_shift } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m3* -m2a* -m4*" } }  */
 /* { dg-final { scan-assembler-not "neg" } } */
 
 unsigned int
Index: gcc/testsuite/gcc.target/sh/pr54089-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-3.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr54089-3.c	(working copy)
@@ -1,9 +1,8 @@
 /* The dynamic shift library functions truncate the shift count to 5 bits.
    Verify that this is taken into account and no extra shift count
    truncations are generated before the library call.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { ! has_dyn_shift } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2" "-m2e*" } } */
 /* { dg-final { scan-assembler-not "and" } } */
 /* { dg-final { scan-assembler-not "#31" } } */
 
Index: gcc/testsuite/gcc.target/sh/pr54089-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-4.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr54089-4.c	(working copy)
@@ -1,12 +1,16 @@
 /* Check that the rotcr instruction is generated when shifting the
-   negated T bit on non-SH2A.  */
+   negated T bit on non-SH2A.
+   On SH2A expect a movrt rotr sequence instead.  */
 /* { dg-do compile }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } }  */
-/* { dg-final { scan-assembler-times "rotcr" 1 } } */
-/* { dg-final { scan-assembler-times "tst" 1 } } */
-/* { dg-final { scan-assembler-times "movt" 1 } } */
 
+/* { dg-final { scan-assembler-times "rotcr" 1 { target { ! sh2a } } } } */
+/* { dg-final { scan-assembler-times "tst" 1 { target { ! sh2a } } } } */
+/* { dg-final { scan-assembler-times "movt" 1 { target { ! sh2a } } } } */
+
+/* { dg-final { scan-assembler-times "movrt" 1 { target { sh2a } } } } */
+/* { dg-final { scan-assembler-times "rotr" 1 { target { sh2a } } } } */
+
 int
 test_00 (int a, int b)
 {
Index: gcc/testsuite/gcc.target/sh/pr54089-5.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54089-5.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr54089-5.c	(working copy)
@@ -1,14 +0,0 @@
-/* Check that the movrt rotr instruction sequence is generated when shifting
-   the negated T bit on SH2A.  */
-/* { dg-do compile }  */
-/* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
-/* { dg-final { scan-assembler-times "movrt" 1 } } */
-/* { dg-final { scan-assembler-times "rotr" 1 } } */
-
-int
-test_00 (int a, int b)
-{
-  int r = a != b;
-  return r << 31;
-}
Index: gcc/testsuite/gcc.target/sh/pr54602-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54602-2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr54602-2.c	(working copy)
@@ -1,9 +1,8 @@
 /* Verify that the delay slot is not stuffed with register pop insns for
    interrupt handler function returns on SH1* and SH2* targets, where the
    rte insn uses the stack pointer.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { stack_save_isr } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2*" } }  */
 /* { dg-final { scan-assembler-times "nop" 1 } } */
 
 int test00 (int a, int b);
Index: gcc/testsuite/gcc.target/sh/pr54602-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54602-3.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr54602-3.c	(working copy)
@@ -1,8 +1,7 @@
 /* Verify that the rte delay slot is not stuffed with register pop insns
    which touch the banked registers r0..r7 on SH3* and SH4* targets.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { banked_r0r7_isr } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m3*" "-m4*" } }  */
 /* { dg-final { scan-assembler-times "nop" 1 } } */
 
 int __attribute__ ((interrupt_handler))
Index: gcc/testsuite/gcc.target/sh/pr54602-4.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54602-4.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr54602-4.c	(working copy)
@@ -1,9 +1,8 @@
 /* Verify that the delay slot is stuffed with register pop insns on SH3* and
    SH4* targets, where the stack pointer is not used by the rte insn.  If
    everything works out, we won't see a nop insn.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { banked_r0r7_isr } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m3*" "-m4*" } }  */
 /* { dg-final { scan-assembler-not "rte\n\tnop" } } */
 
 int test00 (int a, int b);
Index: gcc/testsuite/gcc.target/sh/pr54680.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54680.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr54680.c	(working copy)
@@ -1,9 +1,8 @@
 /* Verify that the fsca input value is not converted to float and then back
    to int.  Notice that we can't count just "lds" insns because mode switches
    use "lds.l".  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { has_fsca } } }  */
 /* { dg-options "-O2 -mfsca -funsafe-math-optimizations -fno-ipa-icf" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fsca" 7 } } */
 /* { dg-final { scan-assembler-times "shad" 1 } } */
 /* { dg-final { scan-assembler-times "lds\tr\[0-9\],fpul" 6 } } */
Index: gcc/testsuite/gcc.target/sh/pr55303-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr55303-1.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr55303-1.c	(working copy)
@@ -1,8 +1,7 @@
 /* Verify that the SH2A clips and clipu instructions are generated as
    expected.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "clips.b" 2 } } */
 /* { dg-final { scan-assembler-times "clips.w" 2 } } */
 /* { dg-final { scan-assembler-times "clipu.b" 2 } } */
Index: gcc/testsuite/gcc.target/sh/pr55303-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr55303-2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr55303-2.c	(working copy)
@@ -1,9 +1,8 @@
 /* Verify that for SH2A smax/smin -> cbranch conversion is done properly
    if the clips insn is not used and the expected comparison insns are
    generated.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "cmp/pl" 4 } } */
 
 int
Index: gcc/testsuite/gcc.target/sh/pr55303-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr55303-3.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr55303-3.c	(working copy)
@@ -1,8 +1,7 @@
 /* Verify that the special case (umin (reg const_int 1)) results in the
    expected instruction sequence on SH2A.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
 /* { dg-final { scan-assembler-times "tst" 1 } } */
 /* { dg-final { scan-assembler-times "movrt" 1 } } */
 
Index: gcc/testsuite/gcc.target/sh/pr56547-1.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr56547-1.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr56547-1.c	(working copy)
@@ -1,9 +1,8 @@
 /* Verify that the fmac insn is used for the expression 'a * b + a' and
    'a * a + a'.
    This assumes that the default compiler setting is -ffp-contract=fast.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O1" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmac" 2 } } */
 
 float
Index: gcc/testsuite/gcc.target/sh/pr56547-2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr56547-2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr56547-2.c	(working copy)
@@ -1,8 +1,7 @@
 /* Verify that the fmac insn is used for the expression 'a * b + a' and
    'a * a + a' when -ffast-math is specified.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { any_fpu } } }  */
 /* { dg-options "-O1 -ffast-math" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
 /* { dg-final { scan-assembler-times "fmac" 2 } } */
 
 float
Index: gcc/testsuite/gcc.target/sh/pr61195.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr61195.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr61195.c	(working copy)
@@ -1,8 +1,6 @@
 /* Verify that we don't switch mode for single moves.  */
-/* { dg-do compile }  */
-/* { dg-require-effective-target hard_float } */
-/* { dg-skip-if "" { *-*-* }  { "mfmovd" } { "" } } */
-/* { dg-final { scan-assembler-not "fpscr" } } */
+/* { dg-do compile { target { any_fpu && { ! fmovd_enabled } } } }  */
+/* { dg-final { scan-assembler-not "fpscr|fpchg" } } */
 
 float *g;
 
Index: gcc/testsuite/gcc.target/sh/pr61996.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr61996.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr61996.c	(working copy)
@@ -1,9 +1,8 @@
 /* Check that the option -musermode has no effect on targets that do not
    support user/privileged mode and that it does not interfere with option
    -matomic-model=soft-imask.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { ! has_privileged } } }  */
 /* { dg-options "-matomic-model=soft-imask" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m1*" "-m2*" } }  */
 
 int
 test (void)
Index: gcc/testsuite/gcc.target/sh/pr6526.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr6526.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pr6526.c	(working copy)
@@ -1,8 +1,8 @@
 /* Check that the XF registers are not clobbered by an integer division
    that is done using double precision FPU division.  */
-/* { dg-do run }  */
+
+/* { dg-do run { target { default_single_fpu && has_xf_regs } } } */
 /* { dg-options "-O1 -mdiv=call-fp" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4*-single" "-m4*-single-only" } }  */
 
 #include <assert.h>
 #include <stdlib.h>
Index: gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c	(working copy)
@@ -3,8 +3,7 @@
    (On SH3* and SH4* r0..r7 are banked)
    Call-saved registers r8..r14 also don't need to be restored.
    To test that we look for register push insns such as 'mov.l r0,@-r15'.  */
-/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1*" "-m2*" "-m5*" } { "" } }  */
+/* { dg-do compile { target { { banked_r0r7_isr } && nonpic } } }  */
 /* { dg-options "-O" }  */
 /* { dg-final { scan-assembler-times "rte" 1 } }  */
 /* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } }  */
Index: gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c	(working copy)
@@ -2,8 +2,7 @@
    The function call will require to load the address first into a register,
    then use that for a jsr or jmp.  It will also need to load a constant
    address in order to load fpscr.  */
-/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-do compile { target { { any_fpu } && nonpic } } }  */
 /* { dg-options "-O" }  */
 /* { dg-final { scan-assembler-times "rte" 1 } }  */
 /* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } }  */
Index: gcc/testsuite/gcc.target/sh/prefetch.c
===================================================================
--- gcc/testsuite/gcc.target/sh/prefetch.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/prefetch.c	(working copy)
@@ -1,9 +1,8 @@
-/* Testcase to check generation of a SH4 and SH2A operand cache prefetch
-   instruction PREF @Rm.  */
-/* { dg-do assemble }  */
+/* Testcase to check generation of the operand cache prefetch instruction
+   PREF @Rm.  */
+/* { dg-do compile { target { has_pref } } }  */
 /* { dg-options "-O0" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" "-m3*" "-m4*" } }  */
-/* { dg-final { scan-assembler "pref"} }  */
+/* { dg-final { scan-assembler "pref" } }  */
 
 void
 opt (void)
Index: gcc/testsuite/gcc.target/sh/rte-delay-slot.c
===================================================================
--- gcc/testsuite/gcc.target/sh/rte-delay-slot.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/rte-delay-slot.c	(working copy)
@@ -1,6 +1,5 @@
-/* { dg-do compile }  */
+/* { dg-do compile { target { stack_save_isr } } }  */
 /* { dg-options "-O2" } */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m1 -m2*" }  */
 /* { dg-final { scan-assembler-not "\trte\t\n\tmov.l\t@r15\\+" } } */
 
 /* This test checks if the compiler generates a pop instruction
Index: gcc/testsuite/gcc.target/sh/sh.exp
===================================================================
--- gcc/testsuite/gcc.target/sh/sh.exp	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh.exp	(working copy)
@@ -42,6 +42,217 @@
     } ""]
 }
 
+# Return 1 if target is SH4A
+proc check_effective_target_sh4a { } {
+    return [check_no_compiler_messages sh4a object {
+	     #ifndef __SH4A__
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if target is big endian
+proc check_effective_target_big_endian { } {
+    return [check_no_compiler_messages big_endian object {
+	     #if __BYTE_ORDER__ != __ORDER_BIG_ENDIAN__
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if target is little endian
+proc check_effective_target_little_endian { } {
+    return [check_no_compiler_messages little_endian object {
+	     #if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if the target has any FPU (single or double precision)
+proc check_effective_target_any_fpu { } {
+    return [check_no_compiler_messages any_fpu object {
+	     #ifndef __SH_FPU_ANY__
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if the target has a double precision FPU which is allowed to be
+# used by the compiler as such.
+proc check_effective_target_double_fpu { } {
+    return [check_no_compiler_messages double_fpu object {
+	     #ifndef __SH_FPU_DOUBLE__
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if the target has a double precision FPU but it is only being used
+# in single precision mode by the compiler
+proc check_effective_target_use_single_only_fpu { } {
+    return [check_no_compiler_messages use_single_only_fpu object {
+	     #if !(defined (__SH2A_SINGLE_ONLY__) \
+		   || defined (__SH4_SINGLE_ONLY__))
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if the target has an FPU and the default mode is single
+proc check_effective_target_default_single_fpu { } {
+    return [check_no_compiler_messages default_single_fpu object {
+	     #if !(defined (__SH2E__) || defined (__SH3E__) \
+		   || defined (__SH2A_SINGLE__) \
+		   || defined (__SH2A_SINGLE_ONLY__) \
+		   || defined (__SH4_SINGLE__) \
+		   || defined (__SH4_SINGLE_ONLY__))
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if the target has no FPU
+proc check_effective_target_no_fpu { } {
+    return [check_no_compiler_messages no_fpu object {
+	     #ifdef __SH_FPU_ANY__
+	     #error ""
+	     #endif
+    } ""]
+}
+
+
+# Return 1 if the target has XF regs
+proc check_effective_target_has_xf_regs { } {
+    return [check_no_compiler_messages has_xf_regs object {
+	     #if !(defined (__SH_FPU_ANY__) \
+		   && (defined (__SH4__) \
+		       || defined (__SH4_SINGLE__) \
+		       || defined (__SH4_SINGLE_ONLY__) \
+		       || defined (__SH4A__)))
+	     #error ""
+	     #endif
+    } ""]
+}
+
+
+# Return 1 if the target can do the fsca insn
+proc check_effective_target_has_fsca { } {
+    return [check_no_compiler_messages has_fsca object {
+	     #if !(defined (__SH_FPU_ANY__) \
+		   && (defined (__SH4__) \
+		       || defined (__SH4_SINGLE__) \
+		       || defined (__SH4_SINGLE_ONLY__) \
+		       || defined (__SH4A__)))
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if the target can do the fsrra insn
+proc check_effective_target_has_fsrra { } {
+    return [check_no_compiler_messages has_fsrra object {
+	     #if !(defined (__SH_FPU_ANY__) \
+		   && (defined (__SH4__) \
+		       || defined (__SH4_SINGLE__) \
+		       || defined (__SH4_SINGLE_ONLY__) \
+		       || defined (__SH4A__)))
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if the target can do the fpchg insn
+proc check_effective_target_has_fpchg { } {
+    return [check_no_compiler_messages has_fpchg object {
+	     #if !(defined (__SH4A__) && defined (__SH_FPU_ANY__) \
+		   && !defined (__SH4_SINGLE_ONLY__))
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if the target can do dynamic shifts
+proc check_effective_target_has_dyn_shift { } {
+    return [check_no_compiler_messages has_dyn_shift object {
+	     #if !(defined (__SH3__) \
+		   || defined (__SH3E__) \
+		   || defined (__SH2A__) \
+		   || defined (__SH4__) \
+		   || defined (__SH4_NOFPU__) \
+		   || defined (__SH4_SINGLE__) \
+		   || defined (__SH4_SINGLE_ONLY__) \
+		   || defined (__SH4A__))
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if the mfmovd option is enabled
+proc check_effective_target_fmovd_enabled { } {
+    return [check_no_compiler_messages fmovd_enabled object {
+	     #ifndef __FMOVD_ENABLED__
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if the target supports privileged mode
+proc check_effective_target_has_privileged { } {
+    return [check_no_compiler_messages has_privileged object {
+	     #if !(defined (__SH3__) \
+		   || defined (__SH3E__) \
+		   || defined (__SH4__) \
+		   || defined (__SH4_NOFPU__) \
+		   || defined (__SH4_SINGLE__) \
+		   || defined (__SH4_SINGLE_ONLY__) \
+		   || defined (__SH4A__))
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if the target supports the prefetch insn
+proc check_effective_target_has_pref { } {
+    return [check_no_compiler_messages has_pref object {
+	     #if !(defined (__SH3__) \
+		   || defined (__SH3E__) \
+		   || defined (__SH4__) \
+		   || defined (__SH4_NOFPU__) \
+		   || defined (__SH4_SINGLE__) \
+		   || defined (__SH4_SINGLE_ONLY__) \
+		   || defined (__SH4A__))
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if target does banked r0..r7 regs type of ISRs
+proc check_effective_target_banked_r0r7_isr { } {
+    return [check_no_compiler_messages banked_r0r7_isr object {
+	     #if !(defined (__SH3__) || defined (__SH3E__) \
+		   || defined (__SH4__) \
+		   || defined (__SH4_SINGLE__) \
+		   || defined (__SH4_SINGLE_ONLY__) \
+		   || defined (__SH4_NOFPU__) \
+		   || defined (__SH4A__))
+	     #error ""
+	     #endif
+    } ""]
+}
+
+# Return 1 if target does stack only type of ISRs
+proc check_effective_target_stack_save_isr { } {
+    return [check_no_compiler_messages stack_save_isr object {
+	     #if !(defined (__SH1__) \
+		   || defined (__SH2__) \
+		   || defined (__SH2E__) \
+		   || defined (__SH2A__))
+	     #error ""
+	     #endif
+    } ""]
+}
+
 # Return 1 if target supports atomic-model=soft-gusa
 proc check_effective_target_atomic_model_soft_gusa_available { } {
     return [check_no_compiler_messages atomic_model_soft_gusa_available object {
Index: gcc/testsuite/gcc.target/sh/sh2a-band.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-band.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-band.c	(working copy)
@@ -1,8 +1,7 @@
 /* Testcase to check generation of a SH2A specific instruction for
    "BAND.B #imm3, @(disp12, Rn)".  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O1 -mbitops" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "band.b"} }  */
 
 volatile struct
Index: gcc/testsuite/gcc.target/sh/sh2a-bclr.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bclr.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-bclr.c	(working copy)
@@ -1,8 +1,7 @@
 /* Testcase to check generation of a SH2A specific instruction
    'BCLR #imm3,Rn'.  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O1" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bclr"} }  */
 
 struct a
Index: gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c	(working copy)
@@ -1,8 +1,7 @@
 /* Testcase to check generation of a SH2A specific instruction
    "BCLR #imm3,@(disp12,Rn)".  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O2 -mbitops" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bclr"} }  */
 /* { dg-final { scan-assembler "bclr.b"} }  */
 
Index: gcc/testsuite/gcc.target/sh/sh2a-bld.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bld.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-bld.c	(working copy)
@@ -4,9 +4,8 @@
     BLD #imm3, Rn
     BLD.B #imm3, @(disp12, Rn)
  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-Os -mbitops" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bld"} }  */
 /* { dg-final { scan-assembler "bld.b"} }  */
 
Index: gcc/testsuite/gcc.target/sh/sh2a-bor.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bor.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-bor.c	(working copy)
@@ -1,8 +1,7 @@
 /* Testcase to check generation of a SH2A specific instruction for
    "BOR.B #imm3, @(disp12, Rn)".  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O1 -mbitops" } */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bor.b"} }  */
 
 volatile struct
Index: gcc/testsuite/gcc.target/sh/sh2a-bset.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bset.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-bset.c	(working copy)
@@ -1,8 +1,7 @@
 /* Testcase to check generation of a SH2A specific instruction
   'BSET #imm3,Rn'.  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O1" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bset"} }  */
 
 struct a
Index: gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c	(working copy)
@@ -1,8 +1,7 @@
 /* Testcase to check generation of a SH2A specific instruction
    "BSET #imm3,@(disp12,Rn)".  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O2 -mbitops" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bset"} }  */
 /* { dg-final { scan-assembler "bset.b"} }  */
 
Index: gcc/testsuite/gcc.target/sh/sh2a-bxor.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-bxor.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-bxor.c	(working copy)
@@ -1,8 +1,7 @@
 /* Testcase to check generation of a SH2A specific instruction for
    "BXOR.B #imm3, @(disp12, Rn)".  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O1 -mbitops" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "bxor.b"} }  */
 
 volatile struct
Index: gcc/testsuite/gcc.target/sh/sh2a-jsrn.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-jsrn.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-jsrn.c	(working copy)
@@ -1,8 +1,7 @@
 /* Testcase to check generation of a SH2A specific instruction for
    'JSR/N @Rm'.  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O0" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "jsr/n"} }  */
 
 void foo(void)
Index: gcc/testsuite/gcc.target/sh/sh2a-movi20s.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-movi20s.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-movi20s.c	(working copy)
@@ -1,7 +1,6 @@
 /* Testcase to check generation of 'MOVI20S #imm20, Rn'.  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O0" } */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "movi20s"} }  */
 
 volatile long la;
Index: gcc/testsuite/gcc.target/sh/sh2a-movrt.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-movrt.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-movrt.c	(working copy)
@@ -1,9 +1,8 @@
 /* Testcase to check generation of a SH2A specific instruction for
    'MOVRT Rn'.  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O1" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
-/* { dg-final { scan-assembler "movrt"} }  */
+/* { dg-final { scan-assembler "movrt" } }  */
 
 int
 foo (void)
Index: gcc/testsuite/gcc.target/sh/sh2a-resbank.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-resbank.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-resbank.c	(working copy)
@@ -1,6 +1,5 @@
 /* Test for resbank attribute.  */
-/* { dg-do assemble }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-final { scan-assembler "resbank" } } */
  
 extern void bar(void);
Index: gcc/testsuite/gcc.target/sh/sh2a-rtsn.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-rtsn.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-rtsn.c	(working copy)
@@ -1,8 +1,7 @@
 /* Testcase to check generation of a SH2A specific instruction for
    'RTS/N'.  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "-O0" }  */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
 /* { dg-final { scan-assembler "rts/n"} }  */
 
 void
Index: gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c	(working copy)
@@ -1,8 +1,7 @@
 /* Testcase to check generation of a SH2A specific,
    TBR relative jump instruction - 'JSR @@(disp8,TBR)'.  */
-/* { dg-do assemble }  */
+/* { dg-do compile { target { sh2a } } }  */
 /* { dg-options "" } */
-/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */
 /* { dg-final { scan-assembler-times "jsr/n\\t@@\\(40,tbr\\)" 1} } */
 /* { dg-final { scan-assembler-times "jsr/n\\t@@\\(72,tbr\\)" 1} } */
  
Index: gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c	(working copy)
@@ -1,7 +1,6 @@
 /* Verify that we generate movua to load unaligned 32-bit values on SH4A.  */
-/* { dg-do run }  */
+/* { dg-do run { target { sh4a } } }  */
 /* { dg-options "-O1 -save-temps -fno-inline" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a*" } }  */
 /* { dg-final { scan-assembler-times "movua.l" 6 } } */
 
 /* Aligned.  */
Index: gcc/testsuite/gcc.target/sh/sh4a-cosf.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh4a-cosf.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh4a-cosf.c	(working copy)
@@ -1,11 +1,13 @@
 /* Verify that we generate single-precision sine and cosine approximate
    (fsca) in fast math mode on SH4A with FPU.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { sh4a && any_fpu } } }  */
 /* { dg-options "-O -ffast-math" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
 /* { dg-final { scan-assembler "fsca" } } */
 
 #include <math.h>
 
-float test(float f) { return cosf(f); }
-
+float
+test (float f)
+{
+  return cosf (f);
+}
Index: gcc/testsuite/gcc.target/sh/sh4a-fsrra.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh4a-fsrra.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh4a-fsrra.c	(working copy)
@@ -1,11 +1,13 @@
 /* Verify that we generate single-precision square root reciprocal
    approximate (fsrra) in fast math mode on SH4A with FPU.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { has_fsrra } } }  */
 /* { dg-options "-O -ffast-math" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
 /* { dg-final { scan-assembler "fsrra" } } */
 
 #include <math.h>
 
-float test(float f) { return 1 / sqrtf(f); }
-
+float
+test (float f)
+{
+  return 1 / sqrtf (f);
+}
Index: gcc/testsuite/gcc.target/sh/sh4a-memmovua.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh4a-memmovua.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh4a-memmovua.c	(working copy)
@@ -1,14 +1,15 @@
 /* Verify that we generate movua to copy unaligned memory regions to
    32-bit-aligned addresses on SH4A.  */
-/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-do compile { target { sh4a } } }  */
 /* { dg-options "-O" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" "-m4a-nofpu" } }  */
 /* { dg-final { scan-assembler-times "movua.l" 2 } } */
 
 #include <string.h>
 
 struct s { int i; char a[10], b[10]; } x;
-int f() {
-  memcpy(x.a, x.b, 10);
+
+int
+f (void)
+{
+  memcpy (x.a, x.b, 10);
 }
-
Index: gcc/testsuite/gcc.target/sh/sh4a-sincosf.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh4a-sincosf.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh4a-sincosf.c	(working copy)
@@ -1,12 +1,14 @@
 /* Verify that we generate a single single-precision sine and cosine
    approximate (fsca) in fast math mode when a function computes both
    sine and cosine.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { sh4a && any_fpu } } }  */
 /* { dg-options "-O -ffast-math" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
 /* { dg-final { scan-assembler-times "fsca" 1 } } */
 
 #include <math.h>
 
-float test(float f) { return sinf(f) + cosf(f); }
-
+float
+test (float f)
+{
+  return sinf (f) + cosf (f);
+}
Index: gcc/testsuite/gcc.target/sh/sh4a-sinf.c
===================================================================
--- gcc/testsuite/gcc.target/sh/sh4a-sinf.c	(revision 227932)
+++ gcc/testsuite/gcc.target/sh/sh4a-sinf.c	(working copy)
@@ -1,11 +1,13 @@
 /* Verify that we generate single-precision sine and cosine approximate
    (fsca) in fast math mode on SH4A with FPU.  */
-/* { dg-do compile }  */
+/* { dg-do compile { target { sh4a && any_fpu } } }  */
 /* { dg-options "-O -ffast-math" } */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
 /* { dg-final { scan-assembler "fsca" } } */
 
 #include <math.h>
 
-float test(float f) { return sinf(f); }
-
+float
+test (float f)
+{
+  return sinf (f);
+}
