From patchwork Fri Sep 18 15:39:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 519399 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2178214029E for ; Sat, 19 Sep 2015 01:39:33 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=VPTvaGZe; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding; q=dns; s=default; b=QVR3Fm+1OCjzD2+M M4AwZuxHvzGbORWgHNOv33dbbZ+yDL8y+ZlAeBA/Ojt7QtgLTOwhehs5MSIsaQ3H sP1vH8h0wJjIXK3qwS4jZ8eVnYuLKdTivyRRmr+z/YCYfTTSLiD1/WDPcvkmFqU0 Sf9B6hIgIrf/AtaR57WFPaINaPQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding; s=default; bh=2eqgCE4KQhjumRWkWGvtBi UkNzs=; b=VPTvaGZe+xiLtF5Ta25t9l/emRHLvlffHMeHATuobReyWo7HRf4STQ r5ghmf7SJAiznNNMkXSRIg5U5CBgkn48i2cvgmxKRpCVa6W8YSu+zGDky6Xva+rh /IESpziWHBeEfddJFkSN+KboGi720SvgnsUWbU00CKJjf6vX+zvmo= Received: (qmail 10472 invoked by alias); 18 Sep 2015 15:39:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 10457 invoked by uid 89); 18 Sep 2015 15:39:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 18 Sep 2015 15:39:24 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-2-Go7TUNAlSYKh7iPJ3uSnXQ-1; Fri, 18 Sep 2015 16:39:19 +0100 Received: from arm.com ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 18 Sep 2015 16:39:18 +0100 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, wschmidt@linux.vnet.ibm.com Subject: [PATCH][RS6000] Migrate from reduc_xxx to reduc_xxx_scal optabs Date: Fri, 18 Sep 2015 16:39:08 +0100 Message-Id: <1442590748-5801-1-git-send-email-alan.lawrence@arm.com> X-MC-Unique: Go7TUNAlSYKh7iPJ3uSnXQ-1 X-IsSubscribed: yes This is a respin of https://gcc.gnu.org/ml/gcc-patches/2014-12/msg01024.html after discovering that patch was broken on power64le - thanks to Bill Schmidt for pointing out that gcc112 is the opposite endianness to gcc110... This time I decided to avoid any funny business with making RTL match other patterns in other .md files, and instead to directly call the relevant expanders. This should thus preserve the codegen of the previous expansion path. Moreover, combining the uplus and splus expansion paths (as addition is the same regardless of signedness) causes some additional examples to be reduced directly via patterns. Bootstrapped + check-g{cc,++,fortran} on powerpc64-none-linux-gnu (--with-cpu=power7) and powerpc64le-none-linux-gnu (--with-cpu=power8). gcc/ChangeLog: * config/rs6000/altivec.md (reduc_splus_): Rename to... (reduc_plus_scal_): ...this, add rs6000_expand_vector_extract. (reduc_uplus_v16qi): Remove. * config/rs6000/vector.md (VEC_reduc_name): Change "splus" to "plus". (reduc__v2df): Remove. (reduc__v4sf): Remove. (reduc__scal_): New. * config/rs6000/vsx.md (vsx_reduc__v2df): Declare gen_ function by removing * prefix. (vsx_reduc__v4sf): Likewise. --- gcc/config/rs6000/altivec.md | 25 ++++++----------------- gcc/config/rs6000/vector.md | 47 ++++++++++++++++++-------------------------- gcc/config/rs6000/vsx.md | 4 ++-- 3 files changed, 27 insertions(+), 49 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 4170f38..93ce1f0 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2648,35 +2648,22 @@ operands[3] = gen_reg_rtx (GET_MODE (operands[0])); }) -(define_expand "reduc_splus_" - [(set (match_operand:VIshort 0 "register_operand" "=v") +(define_expand "reduc_plus_scal_" + [(set (match_operand: 0 "register_operand" "=v") (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")] UNSPEC_REDUC_PLUS))] "TARGET_ALTIVEC" { rtx vzero = gen_reg_rtx (V4SImode); rtx vtmp1 = gen_reg_rtx (V4SImode); - rtx dest = gen_lowpart (V4SImode, operands[0]); + rtx vtmp2 = gen_reg_rtx (mode); + rtx dest = gen_lowpart (V4SImode, vtmp2); + int elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); emit_insn (gen_altivec_vsum4ss (vtmp1, operands[1], vzero)); emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero)); - DONE; -}) - -(define_expand "reduc_uplus_v16qi" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] - UNSPEC_REDUC_PLUS))] - "TARGET_ALTIVEC" -{ - rtx vzero = gen_reg_rtx (V4SImode); - rtx vtmp1 = gen_reg_rtx (V4SImode); - rtx dest = gen_lowpart (V4SImode, operands[0]); - - emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); - emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero)); - emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero)); + rs6000_expand_vector_extract (operands[0], vtmp2, elt); DONE; }) diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 8821dec..d8699c8 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -78,7 +78,7 @@ ;; Vector reduction code iterators (define_code_iterator VEC_reduc [plus smin smax]) -(define_code_attr VEC_reduc_name [(plus "splus") +(define_code_attr VEC_reduc_name [(plus "plus") (smin "smin") (smax "smax")]) @@ -1061,38 +1061,29 @@ "") ;; Vector reduction expanders for VSX - -(define_expand "reduc__v2df" - [(parallel [(set (match_operand:V2DF 0 "vfloat_operand" "") - (VEC_reduc:V2DF - (vec_concat:V2DF - (vec_select:DF - (match_operand:V2DF 1 "vfloat_operand" "") - (parallel [(const_int 1)])) - (vec_select:DF - (match_dup 1) - (parallel [(const_int 0)]))) - (match_dup 1))) - (clobber (match_scratch:V2DF 2 ""))])] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "") - -; The (VEC_reduc:V4SF +; The (VEC_reduc:... ; (op1) -; (unspec:V4SF [(const_int 0)] UNSPEC_REDUC)) +; (unspec:... [(const_int 0)] UNSPEC_REDUC)) ; ; is to allow us to use a code iterator, but not completely list all of the ; vector rotates, etc. to prevent canonicalization -(define_expand "reduc__v4sf" - [(parallel [(set (match_operand:V4SF 0 "vfloat_operand" "") - (VEC_reduc:V4SF - (unspec:V4SF [(const_int 0)] UNSPEC_REDUC) - (match_operand:V4SF 1 "vfloat_operand" ""))) - (clobber (match_scratch:V4SF 2 "")) - (clobber (match_scratch:V4SF 3 ""))])] - "VECTOR_UNIT_VSX_P (V4SFmode)" - "") + +(define_expand "reduc__scal_" + [(match_operand: 0 "register_operand" "") + (VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + (unspec:VEC_F [(const_int 0)] UNSPEC_REDUC))] + "VECTOR_UNIT_VSX_P (mode)" + { + rtx vec = gen_reg_rtx (mode); + rtx elt = BYTES_BIG_ENDIAN + ? gen_int_mode (GET_MODE_NUNITS (mode) - 1, QImode) + : const0_rtx; + emit_insn (gen_vsx_reduc__ (vec, + operand1)); + emit_insn (gen_vsx_extract_ (operand0, vec, elt)); + DONE; + }) ;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 7f366b8..0e110ae 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -2289,7 +2289,7 @@ ;; Vector reduction insns and splitters -(define_insn_and_split "*vsx_reduc__v2df" +(define_insn_and_split "vsx_reduc__v2df" [(set (match_operand:V2DF 0 "vfloat_operand" "=&wd,&?wa,wd,?wa") (VEC_reduc:V2DF (vec_concat:V2DF @@ -2317,7 +2317,7 @@ [(set_attr "length" "8") (set_attr "type" "veccomplex")]) -(define_insn_and_split "*vsx_reduc__v4sf" +(define_insn_and_split "vsx_reduc__v4sf" [(set (match_operand:V4SF 0 "vfloat_operand" "=wf,?wa") (VEC_reduc:V4SF (unspec:V4SF [(const_int 0)] UNSPEC_REDUC)