From patchwork Tue Sep 15 09:14:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 517753 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3FED31402A3 for ; Tue, 15 Sep 2015 19:16:48 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=QUxr3KiH; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; q=dns; s=default; b=WXj kobGZPojeUZaJrZBBwU19y+pQRwwFIZUxaDebJwjEFiaVb+vCYDLMTp4Sxaaso6F DfTTE9Lf7yd8SV3ViNpevxnFILvr7fwdpH6Dvt3mJ5AMO5SSr0D01y7PRkBU2Ih1 4clHAZKitAeMzcXEP8SqEMrj1XVkIMOetcGuiTe4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; s=default; bh=s6PBXAunv 71nRr1K8WrrfgXq1Mo=; b=QUxr3KiHJVIKpwVupJ7DqIXtNrRoNIlll30Htn8O6 B/yvRYk0Z0PCtyyqx6Til50feccN3HMH/DkXxSbaX9DzTuVUcshWa9vvKiNYDO6s WiyR7JBsezYwQya8vUMUIG5QFM+GXQugutPKMYlrQPl2JajjFZXseeZL2m5WfSxy UA= Received: (qmail 51710 invoked by alias); 15 Sep 2015 09:16:12 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 51600 invoked by uid 89); 15 Sep 2015 09:16:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 15 Sep 2015 09:16:09 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-24-2L7AUCNKSKyq9N62_UGBgw-15; Tue, 15 Sep 2015 10:14:58 +0100 Received: from arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 15 Sep 2015 10:14:54 +0100 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: james.greenhalgh@arm.com Subject: [PATCH][AArch64 array_mode 7/8] Combine the expanders using VSTRUCT:nregs Date: Tue, 15 Sep 2015 10:14:42 +0100 Message-Id: <1442308483-21714-8-git-send-email-alan.lawrence@arm.com> In-Reply-To: <1442308483-21714-1-git-send-email-alan.lawrence@arm.com> References: <1440596819-18018-1-git-send-email-alan.lawrence@arm.com> <1442308483-21714-1-git-send-email-alan.lawrence@arm.com> X-MC-Unique: 2L7AUCNKSKyq9N62_UGBgw-15 X-IsSubscribed: yes The previous patches leave ld[234]_lane, st[234]_lane, and ld[234]r expanders all nearly identical, so we can easily parameterize across the number of lanes and combine them. For the ld_lane pattern, I switched from the VCONQ attribute to just using the MODE attribute, this is identical for all the Q-register modes over which we iterate. bootstrapped and check-gcc on aarch64-none-linux-gnu gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_ld2r, aarch64_ld3r, aarch64_ld4r): Combine together, making... (aarch64_simd_ldr): ...this. (aarch64_ld2_lane, aarch64_ld3_lane, aarch64_ld4_lane): Combine together, making... (aarch64_ld_lane): ...this. (aarch64_st2_lane, aarch64_st3_lane, aarch64_st4_lane): Combine together, making... (aarch64_st_lane): ...this. --- gcc/config/aarch64/aarch64-simd.md | 138 +++++++------------------------------ 1 file changed, 23 insertions(+), 115 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index f239ee7..dbe5259 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4381,42 +4381,18 @@ FAIL; }) -(define_expand "aarch64_ld2r" - [(match_operand:OI 0 "register_operand" "=w") +(define_expand "aarch64_ldr" + [(match_operand:VSTRUCT 0 "register_operand" "=w") (match_operand:DI 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) + * ); - emit_insn (gen_aarch64_simd_ld2r (operands[0], mem)); - DONE; -}) - -(define_expand "aarch64_ld3r" - [(match_operand:CI 0 "register_operand" "=w") - (match_operand:DI 1 "register_operand" "w") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); - - emit_insn (gen_aarch64_simd_ld3r (operands[0], mem)); - DONE; -}) - -(define_expand "aarch64_ld4r" - [(match_operand:XI 0 "register_operand" "=w") - (match_operand:DI 1 "register_operand" "w") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 4); - - emit_insn (gen_aarch64_simd_ld4r (operands[0],mem)); + emit_insn (gen_aarch64_simd_ldr (operands[0], + mem)); DONE; }) @@ -4599,62 +4575,26 @@ DONE; }) -(define_expand "aarch64_ld2_lane" - [(match_operand:OI 0 "register_operand" "=w") - (match_operand:DI 1 "register_operand" "w") - (match_operand:OI 2 "register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); - - emit_insn (gen_aarch64_vec_load_lanesoi_lane (operands[0], - mem, - operands[2], - operands[3])); - DONE; -}) - -(define_expand "aarch64_ld3_lane" - [(match_operand:CI 0 "register_operand" "=w") +(define_expand "aarch64_ld_lane" + [(match_operand:VSTRUCT 0 "register_operand" "=w") (match_operand:DI 1 "register_operand" "w") - (match_operand:CI 2 "register_operand" "0") + (match_operand:VSTRUCT 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); - - emit_insn (gen_aarch64_vec_load_lanesci_lane (operands[0], - mem, - operands[2], - operands[3])); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) + * ); + + aarch64_simd_lane_bounds (operands[3], 0, + GET_MODE_NUNITS (mode), + NULL); + emit_insn (gen_aarch64_vec_load_lanes_lane ( + operands[0], mem, operands[2], operands[3])); DONE; }) -(define_expand "aarch64_ld4_lane" - [(match_operand:XI 0 "register_operand" "=w") - (match_operand:DI 1 "register_operand" "w") - (match_operand:XI 2 "register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[1]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 4); - - emit_insn (gen_aarch64_vec_load_lanesxi_lane (operands[0], - mem, - operands[2], - operands[3])); - DONE; -}) - - - ;; Expanders for builtins to extract vector registers from large ;; opaque integer modes. @@ -4882,51 +4822,19 @@ DONE; }) -(define_expand "aarch64_st2_lane" - [(match_operand:DI 0 "register_operand" "r") - (match_operand:OI 1 "register_operand" "w") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) - (match_operand:SI 2 "immediate_operand")] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[0]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); - - emit_insn (gen_aarch64_vec_store_lanesoi_lane (mem, - operands[1], - operands[2])); - DONE; -}) - -(define_expand "aarch64_st3_lane" - [(match_operand:DI 0 "register_operand" "r") - (match_operand:CI 1 "register_operand" "w") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) - (match_operand:SI 2 "immediate_operand")] - "TARGET_SIMD" -{ - rtx mem = gen_rtx_MEM (BLKmode, operands[0]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 3); - - emit_insn (gen_aarch64_vec_store_lanesci_lane (mem, - operands[1], - operands[2])); - DONE; -}) - -(define_expand "aarch64_st4_lane" +(define_expand "aarch64_st_lane" [(match_operand:DI 0 "register_operand" "r") - (match_operand:XI 1 "register_operand" "w") + (match_operand:VSTRUCT 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { rtx mem = gen_rtx_MEM (BLKmode, operands[0]); - set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 4); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) + * ); - emit_insn (gen_aarch64_vec_store_lanesxi_lane (mem, - operands[1], - operands[2])); + emit_insn (gen_aarch64_vec_store_lanes_lane ( + mem, operands[1], operands[2])); DONE; })