From patchwork Wed Aug 26 13:46:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 510872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A29A61401F0 for ; Wed, 26 Aug 2015 23:47:35 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=XcdhQRBc; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=eetbFSGbKaXCopToXfoGtghJdLQFs2xsqFdJMDvwYXqShmTabRfNJ S0CdX/Os06mOLHO0aQOjxjULv6UB6lhm20C855tuTJLKYfg/dnpd/NxzHa3SdGp/ OhMttqoDvYA+27CbbNal4oN67V73d8lGUVzW8mvKEYXLs0/dcrAOyg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=A3qF3JXD7pp0SEA4nNlQ4MV8xAk=; b=XcdhQRBcaPP/vS/m/1fI XtZhMDt4+IEKcgrbF6dFcAo+OZ047KzSU+f+GLoY5hXt8TxUheWqgU2Zwlh+1l6/ RJk5eax1BQ1F+WlXcUHLCIEQdWHE1hkhgtDT9h8b+RwAI49STwWtdAgPTi6z6VMm xlwSSyhIqOMcHvUHENrUiZE= Received: (qmail 38296 invoked by alias); 26 Aug 2015 13:47:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 38211 invoked by uid 89); 26 Aug 2015 13:47:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, NO_DNS_FOR_FROM, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: cam-smtp0.cambridge.arm.com Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.140) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 26 Aug 2015 13:47:11 +0000 Received: from e104536-lin.cambridge.arm.com (e104536-lin.cambridge.arm.com [10.2.207.65]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id t7QDl76i025840; Wed, 26 Aug 2015 14:47:07 +0100 Received: from e104536-lin.cambridge.arm.com (localhost [127.0.0.1]) by e104536-lin.cambridge.arm.com (8.13.8/8.11.6) with ESMTP id t7QDl75v018088; Wed, 26 Aug 2015 14:47:07 +0100 Received: (from alalaw01@localhost) by e104536-lin.cambridge.arm.com (8.13.8/8.13.8/Submit) id t7QDl7OZ018087; Wed, 26 Aug 2015 14:47:07 +0100 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [PATCH][AArch64 array_mode 1/8] Rename vec_store_lanes_lane to aarch64_vec_store_lanes_lane Date: Wed, 26 Aug 2015 14:46:52 +0100 Message-Id: <1440596819-18018-2-git-send-email-alan.lawrence@arm.com> In-Reply-To: <1440596819-18018-1-git-send-email-alan.lawrence@arm.com> References: <1440596819-18018-1-git-send-email-alan.lawrence@arm.com> X-IsSubscribed: yes vec_store_lanes{oi,ci,xi}_lane are not standard pattern names, so using them in aarch64-simd.md is misleading. This adds an aarch64_ prefix to those pattern names, paralleling aarch64_vec_load_lanes_lane. bootstrapped and check-gcc on aarch64-none-linux-gnu gcc/ChangeLog: * config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane): Rename to... (aarch64_vec_store_lanesoi_lane): ...this. (vec_store_lanesci_lane): Rename to... (aarch64_vec_store_lanesci_lane): ...this. (vec_store_lanesxi_lane): Rename to... (aarch64_vec_store_lanesxi_lane): ...this. (aarch64_st2_lane, aarch64_st3_lane, aarch64_st4_lane): Follow renaming. --- gcc/config/aarch64/aarch64-simd.md | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b90f938..3796386 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3956,7 +3956,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesoi_lane" +(define_insn "aarch64_vec_store_lanesoi_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:OI 1 "register_operand" "w") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4051,7 +4051,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesci_lane" +(define_insn "aarch64_vec_store_lanesci_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:CI 1 "register_operand" "w") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4146,7 +4146,7 @@ ) ;; RTL uses GCC vector extension indices, so flip only for assembly. -(define_insn "vec_store_lanesxi_lane" +(define_insn "aarch64_vec_store_lanesxi_lane" [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") (unspec: [(match_operand:XI 1 "register_operand" "w") (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) @@ -4861,9 +4861,9 @@ rtx mem = gen_rtx_MEM (mode, operands[0]); operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesoi_lane (mem, - operands[1], - operands[2])); + emit_insn (gen_aarch64_vec_store_lanesoi_lane (mem, + operands[1], + operands[2])); DONE; }) @@ -4878,9 +4878,9 @@ rtx mem = gen_rtx_MEM (mode, operands[0]); operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesci_lane (mem, - operands[1], - operands[2])); + emit_insn (gen_aarch64_vec_store_lanesci_lane (mem, + operands[1], + operands[2])); DONE; }) @@ -4895,9 +4895,9 @@ rtx mem = gen_rtx_MEM (mode, operands[0]); operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); - emit_insn (gen_vec_store_lanesxi_lane (mem, - operands[1], - operands[2])); + emit_insn (gen_aarch64_vec_store_lanesxi_lane (mem, + operands[1], + operands[2])); DONE; })