From patchwork Tue Aug 25 13:57:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 510504 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 84BE91401CB for ; Tue, 25 Aug 2015 23:57:57 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=YdSBcx+K; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=iJlpThk5sNaWLI/7ilegGa3stiWijwmtycG380H3la8PpaH8OnbtP A1pPLb2eVd12IkE4yWnHxM3r3G5mVG5ykVoKBF4iI5G7Mtw3BdKJ+qx3i8NfbmBo vqyiXlpNccPcBjvfi4T/kNCAhKm7i1+hX8FXxyK4FGiecNGG1oi06I= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=22iwuoaF8q1Uea8EJ3ek7FdBck0=; b=YdSBcx+K8Y32u1Ap90tt AfAsj3T02v3T10oyQOdXe3WKAYpvx7XoWVwjo6ovIxPWUbXI+kfsCIC+bz33ToV5 rkmom0adiPxFWOxFMjInafVIyRbXSyWy3QAPxAzpR1sQII8NAFMjb7037IxQp3xU hcUtSSMd9uDaVA/VYnnjGWg= Received: (qmail 66005 invoked by alias); 25 Aug 2015 13:57:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 65995 invoked by uid 89); 25 Aug 2015 13:57:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, NO_DNS_FOR_FROM, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: cam-smtp0.cambridge.arm.com Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.140) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Tue, 25 Aug 2015 13:57:48 +0000 Received: from e104536-lin.cambridge.arm.com (e104536-lin.cambridge.arm.com [10.2.207.65]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id t7PDviD1017288; Tue, 25 Aug 2015 14:57:45 +0100 Received: from e104536-lin.cambridge.arm.com (localhost [127.0.0.1]) by e104536-lin.cambridge.arm.com (8.13.8/8.11.6) with ESMTP id t7PDvisO007658; Tue, 25 Aug 2015 14:57:44 +0100 Received: (from alalaw01@localhost) by e104536-lin.cambridge.arm.com (8.13.8/8.13.8/Submit) id t7PDvirS007657; Tue, 25 Aug 2015 14:57:44 +0100 From: Alan Lawrence To: gcc-patches@gcc.gnu.org Cc: christophe.lyon@linaro.org, Alan Lawrence Subject: Re: [PATCH 14/15][ARM/AArch64 Testsuite]Add test of vcvt{, _high}_i{f32_f16, f16_f32} Date: Tue, 25 Aug 2015 14:57:23 +0100 Message-Id: <1440511043-7622-1-git-send-email-alan.lawrence@arm.com> In-Reply-To: <55B7670B.1090902@arm.com> References: <55B7670B.1090902@arm.com> X-IsSubscribed: yes Sorry - wrong version posted. The hunk for add_options_for_arm_neon_fp16 has moved to the previous patch! This version also fixes some whitespace issues. gcc/testsuite/ChangeLog: * gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c: New. * lib/target-supports.exp (check_effective_target_arm_neon_fp16_hw_ok): New. --- .../aarch64/advsimd-intrinsics/vcvt_f16.c | 98 ++++++++++++++++++++++ gcc/testsuite/lib/target-supports.exp | 15 ++++ 2 files changed, 113 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c new file mode 100644 index 0000000..a2cfd38 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c @@ -0,0 +1,98 @@ +/* { dg-require-effective-target arm_neon_fp16_hw_ok { target { arm*-*-* } } } */ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" +#include + +/* Expected results for vcvt. */ +VECT_VAR_DECL (expected,hfloat,32,4) [] = { 0x41800000, 0x41700000, + 0x41600000, 0x41500000 }; +VECT_VAR_DECL (expected,hfloat,16,4) [] = { 0x3e00, 0x4100, 0x4300, 0x4480 }; + +/* Expected results for vcvt_high_f32_f16. */ +VECT_VAR_DECL (expected_high,hfloat,32,4) [] = { 0xc1400000, 0xc1300000, + 0xc1200000, 0xc1100000 }; +/* Expected results for vcvt_high_f16_f32. */ +VECT_VAR_DECL (expected_high,hfloat,16,8) [] = { 0x4000, 0x4000, 0x4000, 0x4000, + 0xcc00, 0xcb80, 0xcb00, 0xca80 }; + +void +exec_vcvt (void) +{ + clean_results (); + +#define TEST_MSG vcvt_f32_f16 + { + VECT_VAR_DECL (buffer_src, float, 16, 4) [] = { 16.0, 15.0, 14.0, 13.0 }; + + DECL_VARIABLE (vector_src, float, 16, 4); + + VLOAD (vector_src, buffer_src, , float, f, 16, 4); + DECL_VARIABLE (vector_res, float, 32, 4) = + vcvt_f32_f16 (VECT_VAR (vector_src, float, 16, 4)); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + + CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, ""); + } +#undef TEST_MSG + + clean_results (); + +#define TEST_MSG vcvt_f16_f32 + { + VECT_VAR_DECL (buffer_src, float, 32, 4) [] = { 1.5, 2.5, 3.5, 4.5 }; + DECL_VARIABLE (vector_src, float, 32, 4); + + VLOAD (vector_src, buffer_src, q, float, f, 32, 4); + DECL_VARIABLE (vector_res, float, 16, 4) = + vcvt_f16_f32 (VECT_VAR (vector_src, float, 32, 4)); + vst1_f16 (VECT_VAR (result, float, 16, 4), + VECT_VAR (vector_res, float, 16 ,4)); + + CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected, ""); + } +#undef TEST_MSG + +#if defined (__aarch64__) + clean_results (); + +#define TEST_MSG "vcvt_high_f32_f16" + { + DECL_VARIABLE (vector_src, float, 16, 8); + VLOAD (vector_src, buffer, q, float, f, 16, 8); + DECL_VARIABLE (vector_res, float, 32, 4); + VECT_VAR (vector_res, float, 32, 4) = + vcvt_high_f32_f16 (VECT_VAR (vector_src, float, 16, 8)); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected_high, ""); + } +#undef TEST_MSG + clean_results (); + +#define TEST_MSG "vcvt_high_f16_f32" + { + DECL_VARIABLE (vector_low, float, 16, 4); + VDUP (vector_low, , float, f, 16, 4, 2.0); + + DECL_VARIABLE (vector_src, float, 32, 4); + VLOAD (vector_src, buffer, q, float, f, 32, 4); + + DECL_VARIABLE (vector_res, float, 16, 8) = + vcvt_high_f16_f32 (VECT_VAR (vector_low, float, 16, 4), + VECT_VAR (vector_src, float, 32, 4)); + vst1q_f16 (VECT_VAR (result, float, 16, 8), + VECT_VAR (vector_res, float, 16, 8)); + + CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_high, ""); + } +#endif +} + +int +main (void) +{ + exec_vcvt (); + return 0; +} diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 9aec02d..0a22c95 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2730,6 +2730,21 @@ proc check_effective_target_arm_neon_fp16_ok { } { check_effective_target_arm_neon_fp16_ok_nocache] } +proc check_effective_target_arm_neon_fp16_hw_ok { } { + if {! [check_effective_target_arm_neon_fp16_ok] } { + return 0 + } + global et_arm_neon_fp16_flags + check_runtime_nocache arm_neon_fp16_hw_ok { + int + main (int argc, char **argv) + { + asm ("vcvt.f32.f16 q1, d0"); + return 0; + } + } $et_arm_neon_fp16_flags +} + proc add_options_for_arm_neon_fp16 { flags } { if { ! [check_effective_target_arm_neon_fp16_ok] } { return "$flags"