From patchwork Fri Aug 15 18:18:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Schmidt X-Patchwork-Id: 380402 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5F2C41400B5 for ; Sat, 16 Aug 2014 04:18:34 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:date:content-type:mime-version :content-transfer-encoding; q=dns; s=default; b=G2qobPC2osdIO9Dc FIolYgoVrwfmkmkeDwW2781II/p2JDQKmfJPaVWtg+8r4uTBdZhFYol+KibdLIN9 ov5TwSgyzAMonlcBbAJseMZPfvcyyRmFpgjZOkhScZr8ch0h1W4eEQ3UqXCWq2BB EP0xYGUxSXU7lIm++VqUbKKQJ0c= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:date:content-type:mime-version :content-transfer-encoding; s=default; bh=9FK9RnEOKRmHq8PPhhD6su 63zEE=; b=jZuXwTEFh0HTJofktdbp6Y3kKg1jGybac+XhCvIcV6B+lia//3k+pk Q8DZByxlPy85C/b+sUI7ISnIOOiPIYKAyJS+FssbEKVOwqOSdTXmJnOIB/LhLltg 7qUknOHUD52hduAkkLtVF1F/hdFE6mBmsHA5mPf18fJyF9brdbhAA= Received: (qmail 5856 invoked by alias); 15 Aug 2014 18:18:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5841 invoked by uid 89); 15 Aug 2014 18:18:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e39.co.us.ibm.com Received: from e39.co.us.ibm.com (HELO e39.co.us.ibm.com) (32.97.110.160) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Fri, 15 Aug 2014 18:18:24 +0000 Received: from /spool/local by e39.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 15 Aug 2014 12:18:21 -0600 Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id E9090C90026 for ; Fri, 15 Aug 2014 14:18:12 -0400 (EDT) Received: from d01av02.pok.ibm.com (d01av02.pok.ibm.com [9.56.224.216]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id s7FIIKvY9961910 for ; Fri, 15 Aug 2014 18:18:20 GMT Received: from d01av02.pok.ibm.com (localhost [127.0.0.1]) by d01av02.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s7FIIKM9023584 for ; Fri, 15 Aug 2014 14:18:20 -0400 Received: from [9.50.19.136] ([9.50.19.136]) by d01av02.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s7FIIJKZ023492 for ; Fri, 15 Aug 2014 14:18:20 -0400 Message-ID: <1408126712.25590.12.camel@gnopaine> Subject: [PATCH, rs6000] Add __VEC_ELEMENT_REG_ORDER__ builtin define for PowerPC From: Bill Schmidt To: gcc-patches@gcc.gnu.org Date: Fri, 15 Aug 2014 13:18:32 -0500 Mime-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14081518-9332-0000-0000-000001B4A7B5 X-IsSubscribed: yes Hi, This adds a macro to indicate the order in which vector elements appear in a register on PowerPC. Elements may appear in right-to-left order for little endian, or in left-to-right order for big endian and when -maltivec=be is selected for little endian. The same macro is being implemented in the IBM XL compilers. Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions. Verified the new macro takes on the correct value in the circumstances listed above. Is this ok for trunk? It would be preferable to backport this to GCC 4.9 as well. Thanks, Bill 2014-08-15 Bill Schmidt * conifg/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Provide builtin define __VEC_ELEMENT_REG_ORDER__. Index: gcc/config/rs6000/rs6000-c.c =================================================================== --- gcc/config/rs6000/rs6000-c.c (revision 214025) +++ gcc/config/rs6000/rs6000-c.c (working copy) @@ -497,6 +497,12 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile) break; } + /* Vector element order. */ + if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) + builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__"); + else + builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__"); + /* Let the compiled code know if 'f' class registers will not be available. */ if (TARGET_SOFT_FLOAT || !TARGET_FPRS) builtin_define ("__NO_FPRS__");