From patchwork Mon Apr 21 14:01:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Schmidt X-Patchwork-Id: 340869 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2EB831400FF for ; Tue, 22 Apr 2014 11:08:09 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=kqv UQfP5aqCXObu1cCwc5Y5Gz2x/mdfDA8mrnIIymqtxwCb6lgZ0PwX6bh/0bFAhdoL kUFc/NN9SfQP2/f/dDJ39v25GKcvPxiHED6QxJwSujx9FzMPVrid7h+h0jfq6mw4 JNY8FXtNAR6P7Npp5bz3M6sW695cP9zBlPNk86tk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; s=default; bh=HgG88enta Twfg6oi1WXIAtdufnA=; b=GzK/1Wf97zRcEh6uB9KgTbfu1bN9zxI1XT3VpnHBK cMPxnmIHJ/AJtNEfEn5RI390ScXTGbNz6QmRYV4eqaUaS/D1f8lt2vfQSHDBcUdC KP7a0f10BxO+spzyHRA1U8It9aOf1stUgs7LBSdYyIvpEDH3QfGbMT+agd0FK9LG f8= Received: (qmail 5365 invoked by alias); 21 Apr 2014 14:01:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5353 invoked by uid 89); 21 Apr 2014 14:01:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.0 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e9.ny.us.ibm.com Received: from e9.ny.us.ibm.com (HELO e9.ny.us.ibm.com) (32.97.182.139) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Mon, 21 Apr 2014 14:01:23 +0000 Received: from /spool/local by e9.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 21 Apr 2014 10:01:19 -0400 Received: from b01cxnp22034.gho.pok.ibm.com (b01cxnp22034.gho.pok.ibm.com [9.57.198.24]) by d01dlp02.pok.ibm.com (Postfix) with ESMTP id 400A26E801B for ; Mon, 21 Apr 2014 10:01:12 -0400 (EDT) Received: from d01av04.pok.ibm.com (d01av04.pok.ibm.com [9.56.224.64]) by b01cxnp22034.gho.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s3LE1IQ053870692 for ; Mon, 21 Apr 2014 14:01:18 GMT Received: from d01av04.pok.ibm.com (localhost [127.0.0.1]) by d01av04.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s3LE1HdK017747 for ; Mon, 21 Apr 2014 10:01:17 -0400 Received: from [9.49.157.136] (sig-9-49-157-136.mts.ibm.com [9.49.157.136]) by d01av04.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s3LE18V5016524; Mon, 21 Apr 2014 10:01:08 -0400 Message-ID: <1398088880.19378.28.camel@gnopaine> Subject: [PATCH] Simplify a VEC_SELECT fed by its own inverse From: Bill Schmidt To: gcc-patches@gcc.gnu.org Cc: ebotcazou@libertysurf.fr, rth@redhat.com Date: Mon, 21 Apr 2014 09:01:20 -0500 Mime-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14042114-7182-0000-0000-00000A655F70 X-IsSubscribed: yes Hi, This patch adds a small RTL simplification for the case where the first operand to a VEC_SELECT is another VEC_SELECT with an inverse selection function. E.g., (vec_select:V4SF (vec_select:V4SF (OP:V4SF) (parallel [2 3 0 1])) (parallel [2 3 0 1])) may be simplified to (OP:V4SF). This comes up in practice on powerpc64le-linux-gnu because of the characteristics of certain loads and stores in the Power7 and later ISAs. When running in little endian modes, one of these loads must be followed by a permute to reorder the vector elements, and one of these stores must be preceded by a permute to once again reorder them. Thus a simple copy may end up with two permutes whose effect cancels each other out. The patch ensures those redundancies are detected and removed. Note that it would be possible to do a more general transformation here, in which any vec_select feeding another could be replaced by a vec_select performing the composite function of the other two. I have not done this because I am unaware of this situation arising in practice. If it's desirable, I can extend the patch in this direction. Bootstrapped and tested on powerpc64[,le]-unknown-linux-gnu with no regressions. Is this ok for trunk? Thanks, Bill [gcc] 2014-04-21 Bill Schmidt * simplify-rtx.c (simplify_binary_operation_1): Optimize case of nested VEC_SELECTs that are inverses of each other. [gcc/testsuite] 2014-04-21 Bill Schmidt * gcc.target/powerpc/vsxcopy.c: New test. Index: gcc/simplify-rtx.c =================================================================== --- gcc/simplify-rtx.c (revision 209516) +++ gcc/simplify-rtx.c (working copy) @@ -3673,6 +3673,34 @@ simplify_binary_operation_1 (enum rtx_code code, e } } + /* If we have two nested selects that are inverses of each + other, replace them with the source operand. */ + if (GET_CODE (trueop0) == VEC_SELECT) + { + enum machine_mode reg_mode = GET_MODE (XEXP (trueop0, 0)); + rtx op0_subop1 = XEXP (trueop0, 1); + gcc_assert (VECTOR_MODE_P (reg_mode)); + gcc_assert (GET_MODE_INNER (mode) == GET_MODE_INNER (reg_mode)); + gcc_assert (GET_CODE (op0_subop1) == PARALLEL); + + if (XVECLEN (trueop1, 0) == XVECLEN (op0_subop1, 0)) + { + /* Apply the second ordering vector to the first. + If the result is { 0, 1, ..., n-1 } then the + two VEC_SELECTs cancel. */ + for (int i = 0; i < XVECLEN (trueop1, 0); ++i) + { + rtx x = XVECEXP (trueop1, 0, i); + gcc_assert (CONST_INT_P (x)); + rtx y = XVECEXP (op0_subop1, 0, INTVAL (x)); + gcc_assert (CONST_INT_P (y)); + if (i != INTVAL (y)) + return 0; + } + return XEXP (trueop0, 0); + } + } + return 0; case VEC_CONCAT: { Index: gcc/testsuite/gcc.target/powerpc/vsxcopy.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/vsxcopy.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/vsxcopy.c (working copy) @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc64*-*-* } } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O1" } */ +/* { dg-final { scan-assembler "lxvd2x" } } */ +/* { dg-final { scan-assembler "stxvd2x" } } */ +/* { dg-final { scan-assembler-not "xxpermdi" } } */ + +typedef float vecf __attribute__ ((vector_size (16))); +extern vecf j, k; + +void fun (void) +{ + j = k; +} +