From patchwork Sun Feb 23 03:25:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bill Schmidt X-Patchwork-Id: 323272 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7446D2C030A for ; Sun, 23 Feb 2014 14:26:01 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=K/C c/F3n6/b85ed0WxUC4YQpYCriWMyymH9bfRlfDzCoEvzWkfEZbnBv/wuVKdwxR2M 8aNRi2ACeOk8NKwCsjxK01TANyTYVpiD8n62cFWy78n6Ko82tDtGWKZaUJ5y8yf2 wKNF3kq9aqTzIeavcYPRW0p+ZEIEaP0yMTWveGA8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:cc:date:content-type :content-transfer-encoding:mime-version; s=default; bh=bHL+95LNu lMF7n8cnMVyqYJLNts=; b=S4JzglO1i8soxoXBtayxd2uEs+kCVA+Oc6gECvdu4 8f8NCnZZpYWJJkYzJKECFLlf/3FH9zIPJCxqovwbQh9+d9A5E7kFU4VwXN8tf/vB WZ9F10lSZWP/GL+ikBvjSh+OsaekFRqyyWHe6gGThQAp1VmC6KgHQrGYV6kgOyn5 pw= Received: (qmail 20306 invoked by alias); 23 Feb 2014 03:25:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 20288 invoked by uid 89); 23 Feb 2014 03:25:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.1 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e28smtp03.in.ibm.com Received: from e28smtp03.in.ibm.com (HELO e28smtp03.in.ibm.com) (122.248.162.3) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Sun, 23 Feb 2014 03:25:45 +0000 Received: from /spool/local by e28smtp03.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Sun, 23 Feb 2014 08:55:36 +0530 Received: from d28relay01.in.ibm.com (d28relay01.in.ibm.com [9.184.220.58]) by d28dlp03.in.ibm.com (Postfix) with ESMTP id 81DFE1258053 for ; Sun, 23 Feb 2014 08:57:38 +0530 (IST) Received: from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63]) by d28relay01.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s1N3POvO65732642 for ; Sun, 23 Feb 2014 08:55:25 +0530 Received: from d28av01.in.ibm.com (localhost [127.0.0.1]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s1N3PZDR007747 for ; Sun, 23 Feb 2014 08:55:35 +0530 Received: from [9.77.131.26] (sig-9-77-131-26.mts.ibm.com [9.77.131.26]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s1N3PWAs007649; Sun, 23 Feb 2014 08:55:34 +0530 Message-ID: <1393125955.20991.62.camel@gnopaine> Subject: [PATCH,rs6000] Add -maltivec=be support for vec_lde and vec_ste From: Bill Schmidt To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com Date: Sat, 22 Feb 2014 21:25:55 -0600 Mime-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14022303-3864-0000-0000-00000C921AF3 X-IsSubscribed: yes Hi, This patch adds -maltivec=be support for vec_lde and vec_ste, similarly to what was done for vec_ld, vec_st, vec_ldl, and vec_stl. Much of the same infrastructure is used. Because the insn pattern for vec_ste is formed slightly differently than the ones for vec_st and vec_stl, we can't reuse altivec_expand_stvx_be in this case (but altivec_expand_lvx_be works fine for vec_lde). There are four new test cases, covering correct behavior for all appropriate vector types for BE, LE, and LE with -maltivec=be. Bootstrapped and tested on powerpc64{,le}-unknown-linux-gnu with no regressions. Is this ok for trunk? Thanks, Bill gcc: 2014-02-22 Bill Schmidt * config/rs6000/altivec.md (altivec_lvex): Replace define_insn with define_expand and new define_insn *altivec_lvex_internal. (altivec_stvex): Replace define_insn with define_expand and new define_insn *altivec_stvex_internal. * config/rs6000/rs6000-protos.h (altivec_expand_stvex_be): New prototype. * config/rs6000/rs6000.c (altivec_expand_lvx_be): Document use by lve*x built-ins. (altivec_expand_stvex_be): New function. gcc/testsuite: 2014-02-22 Bill Schmidt * testsuite/gcc.dg/vmx/lde.c: New test. * testsuite/gcc.dg/vmx/lde-be-order.c: New test. * testsuite/gcc.dg/vmx/ste.c: New test. * testsuite/gcc.dg/vmx/ste-be-order.c: New test. Index: gcc/config/rs6000/altivec.md =================================================================== --- gcc/config/rs6000/altivec.md (revision 208022) +++ gcc/config/rs6000/altivec.md (working copy) @@ -2325,12 +2325,26 @@ ;; Parallel some of the LVE* and STV*'s with unspecs because some have ;; identical rtl but different instructions-- and gcc gets confused. -(define_insn "altivec_lvex" +(define_expand "altivec_lvex" [(parallel [(set (match_operand:VI 0 "register_operand" "=v") (match_operand:VI 1 "memory_operand" "Z")) (unspec [(const_int 0)] UNSPEC_LVE)])] "TARGET_ALTIVEC" +{ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + altivec_expand_lvx_be (operands[0], operands[1], mode, UNSPEC_LVE); + DONE; + } +}) + +(define_insn "*altivec_lvex_internal" + [(parallel + [(set (match_operand:VI 0 "register_operand" "=v") + (match_operand:VI 1 "memory_operand" "Z")) + (unspec [(const_int 0)] UNSPEC_LVE)])] + "TARGET_ALTIVEC" "lvex %0,%y1" [(set_attr "type" "vecload")]) @@ -2435,10 +2449,22 @@ "stvxl %1,%y0" [(set_attr "type" "vecstore")]) -(define_insn "altivec_stvex" +(define_expand "altivec_stvex" [(set (match_operand: 0 "memory_operand" "=Z") (unspec: [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))] "TARGET_ALTIVEC" +{ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + altivec_expand_stvex_be (operands[0], operands[1], mode, UNSPEC_STVE); + DONE; + } +}) + +(define_insn "*altivec_stvex_internal" + [(set (match_operand: 0 "memory_operand" "=Z") + (unspec: [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))] + "TARGET_ALTIVEC" "stvex %1,%y0" [(set_attr "type" "vecstore")]) Index: gcc/config/rs6000/rs6000-protos.h =================================================================== --- gcc/config/rs6000/rs6000-protos.h (revision 208022) +++ gcc/config/rs6000/rs6000-protos.h (working copy) @@ -60,6 +60,7 @@ extern void altivec_expand_vec_perm_le (rtx op[4]) extern bool rs6000_expand_vec_perm_const (rtx op[4]); extern void altivec_expand_lvx_be (rtx, rtx, enum machine_mode, unsigned); extern void altivec_expand_stvx_be (rtx, rtx, enum machine_mode, unsigned); +extern void altivec_expand_stvex_be (rtx, rtx, enum machine_mode, unsigned); extern void rs6000_expand_extract_even (rtx, rtx, rtx); extern void rs6000_expand_interleave (rtx, rtx, rtx, bool); extern void build_mask64_2_operands (rtx, rtx *); Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 208022) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -11779,7 +11779,7 @@ swap_selector_for_mode (enum machine_mode mode) return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm))); } -/* Generate code for an "lvx" or "lvxl" built-in for a little endian target +/* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target with -maltivec=be specified. Issue the load followed by an element-reversing permute. */ void @@ -11816,6 +11816,23 @@ altivec_expand_stvx_be (rtx op0, rtx op1, enum mac emit_insn (par); } +/* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be + specified. Issue the store preceded by an element-reversing permute. */ +void +altivec_expand_stvex_be (rtx op0, rtx op1, enum machine_mode mode, unsigned unspec) +{ + enum machine_mode inner_mode = GET_MODE_INNER (mode); + rtx tmp = gen_reg_rtx (mode); + rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec); + rtx sel = swap_selector_for_mode (mode); + rtx vperm; + + gcc_assert (REG_P (op1)); + vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM); + emit_insn (gen_rtx_SET (VOIDmode, tmp, vperm)); + emit_insn (gen_rtx_SET (VOIDmode, op0, stvx)); +} + static rtx altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk) { Index: gcc/testsuite/gcc.dg/vmx/lde-be-order.c =================================================================== --- gcc/testsuite/gcc.dg/vmx/lde-be-order.c (revision 0) +++ gcc/testsuite/gcc.dg/vmx/lde-be-order.c (working copy) @@ -0,0 +1,73 @@ +/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */ + +#include "harness.h" + +static unsigned char svuc[16] __attribute__ ((aligned (16))); +static signed char svsc[16] __attribute__ ((aligned (16))); +static unsigned short svus[8] __attribute__ ((aligned (16))); +static signed short svss[8] __attribute__ ((aligned (16))); +static unsigned int svui[4] __attribute__ ((aligned (16))); +static signed int svsi[4] __attribute__ ((aligned (16))); +static float svf[4] __attribute__ ((aligned (16))); + +static void init () +{ + int i; +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + for (i = 15; i >= 0; --i) +#else + for (i = 0; i < 16; ++i) +#endif + { + svuc[i] = i; + svsc[i] = i - 8; + } +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + for (i = 7; i >= 0; --i) +#else + for (i = 0; i < 8; ++i) +#endif + { + svus[i] = i; + svss[i] = i - 4; + } +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + for (i = 3; i >= 0; --i) +#else + for (i = 0; i < 4; ++i) +#endif + { + svui[i] = i; + svsi[i] = i - 2; + svf[i] = i * 1.0f; + } +} + +static void test () +{ + vector unsigned char vuc; + vector signed char vsc; + vector unsigned short vus; + vector signed short vss; + vector unsigned int vui; + vector signed int vsi; + vector float vf; + + init (); + + vuc = vec_lde (9*1, (unsigned char *)svuc); + vsc = vec_lde (14*1, (signed char *)svsc); + vus = vec_lde (7*2, (unsigned short *)svus); + vss = vec_lde (1*2, (signed short *)svss); + vui = vec_lde (3*4, (unsigned int *)svui); + vsi = vec_lde (2*4, (signed int *)svsi); + vf = vec_lde (0*4, (float *)svf); + + check (vec_extract (vuc, 9) == 9, "vuc"); + check (vec_extract (vsc, 14) == 6, "vsc"); + check (vec_extract (vus, 7) == 7, "vus"); + check (vec_extract (vss, 1) == -3, "vss"); + check (vec_extract (vui, 3) == 3, "vui"); + check (vec_extract (vsi, 2) == 0, "vsi"); + check (vec_extract (vf, 0) == 0.0, "vf"); +} Index: gcc/testsuite/gcc.dg/vmx/lde.c =================================================================== --- gcc/testsuite/gcc.dg/vmx/lde.c (revision 0) +++ gcc/testsuite/gcc.dg/vmx/lde.c (working copy) @@ -0,0 +1,59 @@ +#include "harness.h" + +static unsigned char svuc[16] __attribute__ ((aligned (16))); +static signed char svsc[16] __attribute__ ((aligned (16))); +static unsigned short svus[8] __attribute__ ((aligned (16))); +static signed short svss[8] __attribute__ ((aligned (16))); +static unsigned int svui[4] __attribute__ ((aligned (16))); +static signed int svsi[4] __attribute__ ((aligned (16))); +static float svf[4] __attribute__ ((aligned (16))); + +static void init () +{ + unsigned int i; + for (i = 0; i < 16; ++i) + { + svuc[i] = i; + svsc[i] = i - 8; + } + for (i = 0; i < 8; ++i) + { + svus[i] = i; + svss[i] = i - 4; + } + for (i = 0; i < 4; ++i) + { + svui[i] = i; + svsi[i] = i - 2; + svf[i] = i * 1.0f; + } +} + +static void test () +{ + vector unsigned char vuc; + vector signed char vsc; + vector unsigned short vus; + vector signed short vss; + vector unsigned int vui; + vector signed int vsi; + vector float vf; + + init (); + + vuc = vec_lde (9*1, (unsigned char *)svuc); + vsc = vec_lde (14*1, (signed char *)svsc); + vus = vec_lde (7*2, (unsigned short *)svus); + vss = vec_lde (1*2, (signed short *)svss); + vui = vec_lde (3*4, (unsigned int *)svui); + vsi = vec_lde (2*4, (signed int *)svsi); + vf = vec_lde (0*4, (float *)svf); + + check (vec_extract (vuc, 9) == 9, "vuc"); + check (vec_extract (vsc, 14) == 6, "vsc"); + check (vec_extract (vus, 7) == 7, "vus"); + check (vec_extract (vss, 1) == -3, "vss"); + check (vec_extract (vui, 3) == 3, "vui"); + check (vec_extract (vsi, 2) == 0, "vsi"); + check (vec_extract (vf, 0) == 0.0, "vf"); +} Index: gcc/testsuite/gcc.dg/vmx/ste-be-order.c =================================================================== --- gcc/testsuite/gcc.dg/vmx/ste-be-order.c (revision 0) +++ gcc/testsuite/gcc.dg/vmx/ste-be-order.c (working copy) @@ -0,0 +1,53 @@ +/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */ + +#include "harness.h" + +static unsigned char svuc[16] __attribute__ ((aligned (16))); +static signed char svsc[16] __attribute__ ((aligned (16))); +static unsigned short svus[8] __attribute__ ((aligned (16))); +static signed short svss[8] __attribute__ ((aligned (16))); +static unsigned int svui[4] __attribute__ ((aligned (16))); +static signed int svsi[4] __attribute__ ((aligned (16))); +static float svf[4] __attribute__ ((aligned (16))); + +static void check_arrays () +{ + check (svuc[9] == 9, "svuc"); + check (svsc[14] == 6, "svsc"); + check (svus[7] == 7, "svus"); + check (svss[1] == -3, "svss"); + check (svui[3] == 3, "svui"); + check (svsi[2] == 0, "svsi"); + check (svf[0] == 0.0, "svf"); +} + +static void test () +{ +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + vector unsigned char vuc = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0}; + vector signed char vsc = {7,6,5,4,3,2,1,0,-1,-2,-3,-4,-5,-6,-7,-8}; + vector unsigned short vus = {7,6,5,4,3,2,1,0}; + vector signed short vss = {3,2,1,0,-1,-2,-3,-4}; + vector unsigned int vui = {3,2,1,0}; + vector signed int vsi = {1,0,-1,-2}; + vector float vf = {3.0,2.0,1.0,0.0}; +#else + vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7}; + vector unsigned short vus = {0,1,2,3,4,5,6,7}; + vector signed short vss = {-4,-3,-2,-1,0,1,2,3}; + vector unsigned int vui = {0,1,2,3}; + vector signed int vsi = {-2,-1,0,1}; + vector float vf = {0.0,1.0,2.0,3.0}; +#endif + + vec_ste (vuc, 9*1, (unsigned char *)svuc); + vec_ste (vsc, 14*1, (signed char *)svsc); + vec_ste (vus, 7*2, (unsigned short *)svus); + vec_ste (vss, 1*2, (signed short *)svss); + vec_ste (vui, 3*4, (unsigned int *)svui); + vec_ste (vsi, 2*4, (signed int *)svsi); + vec_ste (vf, 0*4, (float *)svf); + + check_arrays (); +} Index: gcc/testsuite/gcc.dg/vmx/ste.c =================================================================== --- gcc/testsuite/gcc.dg/vmx/ste.c (revision 0) +++ gcc/testsuite/gcc.dg/vmx/ste.c (working copy) @@ -0,0 +1,41 @@ +#include "harness.h" + +static unsigned char svuc[16] __attribute__ ((aligned (16))); +static signed char svsc[16] __attribute__ ((aligned (16))); +static unsigned short svus[8] __attribute__ ((aligned (16))); +static signed short svss[8] __attribute__ ((aligned (16))); +static unsigned int svui[4] __attribute__ ((aligned (16))); +static signed int svsi[4] __attribute__ ((aligned (16))); +static float svf[4] __attribute__ ((aligned (16))); + +static void check_arrays () +{ + check (svuc[9] == 9, "svuc"); + check (svsc[14] == 6, "svsc"); + check (svus[7] == 7, "svus"); + check (svss[1] == -3, "svss"); + check (svui[3] == 3, "svui"); + check (svsi[2] == 0, "svsi"); + check (svf[0] == 0.0, "svf"); +} + +static void test () +{ + vector unsigned char vuc = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + vector signed char vsc = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7}; + vector unsigned short vus = {0,1,2,3,4,5,6,7}; + vector signed short vss = {-4,-3,-2,-1,0,1,2,3}; + vector unsigned int vui = {0,1,2,3}; + vector signed int vsi = {-2,-1,0,1}; + vector float vf = {0.0,1.0,2.0,3.0}; + + vec_ste (vuc, 9*1, (unsigned char *)svuc); + vec_ste (vsc, 14*1, (signed char *)svsc); + vec_ste (vus, 7*2, (unsigned short *)svus); + vec_ste (vss, 1*2, (signed short *)svss); + vec_ste (vui, 3*4, (unsigned int *)svui); + vec_ste (vsi, 2*4, (signed int *)svsi); + vec_ste (vf, 0*4, (float *)svf); + + check_arrays (); +}